Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49315	0	0
CgEnOn_A	2147483647	40124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49315	0	0
T1	456896	3	0	0
T2	5115755	524	0	0
T3	0	123	0	0
T5	15341	59	0	0
T6	61176	3	0	0
T10	0	5	0	0
T17	36337	43	0	0
T18	196382	3	0	0
T19	62078	3	0	0
T20	84901	3	0	0
T21	21776	3	0	0
T22	19633	3	0	0
T26	0	5	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	12	0	0
T41	0	1	0	0
T61	18898	0	0	0
T166	0	19	0	0
T167	0	30	0	0
T168	0	16	0	0
T169	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40124	0	0
T2	5115755	740	0	0
T3	0	725	0	0
T5	15341	75	0	0
T6	61176	0	0	0
T10	0	4	0	0
T17	36337	60	0	0
T18	196382	0	0	0
T19	62078	0	0	0
T20	84901	0	0	0
T21	21776	0	0	0
T22	19633	0	0	0
T26	0	5	0	0
T36	0	5	0	0
T37	0	16	0	0
T38	0	24	0	0
T41	0	1	0	0
T61	23931	0	0	0
T67	0	10	0	0
T102	0	42	0	0
T166	0	37	0	0
T167	0	64	0	0
T168	0	36	0	0
T169	0	21	0	0
T170	0	10	0	0
T171	0	3	0	0
T172	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255359622	173	0	0
CgEnOn_A	255359622	173	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255359622	173	0	0
T2	496693	1	0	0
T5	676	6	0	0
T6	2966	0	0	0
T10	0	1	0	0
T17	1753	4	0	0
T18	9085	0	0	0
T19	2939	0	0	0
T20	5752	0	0	0
T21	1025	0	0	0
T22	903	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	1142	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255359622	173	0	0
T2	496693	1	0	0
T5	676	6	0	0
T6	2966	0	0	0
T10	0	1	0	0
T17	1753	4	0	0
T18	9085	0	0	0
T19	2939	0	0	0
T20	5752	0	0	0
T21	1025	0	0	0
T22	903	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	1142	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127679182	173	0	0
CgEnOn_A	127679182	173	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	511072462	173	0	0
CgEnOn_A	511072462	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072462	173	0	0
T2	993946	1	0	0
T5	1430	6	0	0
T6	5636	0	0	0
T10	0	1	0	0
T17	3543	4	0	0
T18	18290	0	0	0
T19	5751	0	0	0
T20	7075	0	0	0
T21	2020	0	0	0
T22	1831	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	2213	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072462	167	0	0
T2	993946	0	0	0
T5	1430	6	0	0
T6	5636	0	0	0
T17	3543	4	0	0
T18	18290	0	0	0
T19	5751	0	0	0
T20	7075	0	0	0
T21	2020	0	0	0
T22	1831	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	2213	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	2	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	170	0	0
CgEnOn_A	544414618	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	170	0	0
T2	105976	0	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	168	0	0
T2	105976	0	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127679182	173	0	0
CgEnOn_A	127679182	173	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	170	0	0
CgEnOn_A	544414618	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	170	0	0
T2	105976	0	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	168	0	0
T2	105976	0	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Unreachable
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127679182	173	0	0
CgEnOn_A	127679182	173	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	173	0	0
T2	248345	1	0	0
T5	338	6	0	0
T6	1482	0	0	0
T10	0	1	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T61	571	0	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255359622	7890	0	0
CgEnOn_A	255359622	5600	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255359622	7890	0	0
T1	101519	1	0	0
T2	496693	133	0	0
T5	676	7	0	0
T6	2966	1	0	0
T17	1753	5	0	0
T18	9085	1	0	0
T19	2939	1	0	0
T20	5752	1	0	0
T21	1025	1	0	0
T22	903	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255359622	5600	0	0
T2	496693	125	0	0
T3	0	121	0	0
T5	676	6	0	0
T6	2966	0	0	0
T17	1753	4	0	0
T18	9085	0	0	0
T19	2939	0	0	0
T20	5752	0	0	0
T21	1025	0	0	0
T22	903	0	0	0
T38	0	2	0	0
T61	1142	0	0	0
T67	0	2	0	0
T102	0	11	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127679182	7792	0	0
CgEnOn_A	127679182	5502	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	7792	0	0
T1	50759	1	0	0
T2	248345	134	0	0
T5	338	7	0	0
T6	1482	1	0	0
T17	876	5	0	0
T18	4542	1	0	0
T19	1469	1	0	0
T20	2874	1	0	0
T21	513	1	0	0
T22	452	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679182	5502	0	0
T2	248345	126	0	0
T3	0	116	0	0
T5	338	6	0	0
T6	1482	0	0	0
T17	876	4	0	0
T18	4542	0	0	0
T19	1469	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T38	0	2	0	0
T61	571	0	0	0
T67	0	3	0	0
T102	0	10	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	511072462	7901	0	0
CgEnOn_A	511072462	5605	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072462	7901	0	0
T1	203075	1	0	0
T2	993946	135	0	0
T5	1430	7	0	0
T6	5636	1	0	0
T17	3543	5	0	0
T18	18290	1	0	0
T19	5751	1	0	0
T20	7075	1	0	0
T21	2020	1	0	0
T22	1831	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072462	5605	0	0
T2	993946	126	0	0
T3	0	123	0	0
T5	1430	6	0	0
T6	5636	0	0	0
T17	3543	4	0	0
T18	18290	0	0	0
T19	5751	0	0	0
T20	7075	0	0	0
T21	2020	0	0	0
T22	1831	0	0	0
T38	0	2	0	0
T61	2213	0	0	0
T67	0	3	0	0
T102	0	11	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	261426203	7860	0	0
CgEnOn_A	261426203	5563	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261426203	7860	0	0
T1	101543	1	0	0
T2	505241	138	0	0
T5	765	4	0	0
T6	2818	1	0	0
T17	1709	5	0	0
T18	9146	1	0	0
T19	2876	1	0	0
T20	3537	1	0	0
T21	1010	1	0	0
T22	915	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261426203	5563	0	0
T2	505241	129	0	0
T3	0	113	0	0
T5	765	3	0	0
T6	2818	0	0	0
T17	1709	4	0	0
T18	9146	0	0	0
T19	2876	0	0	0
T20	3537	0	0	0
T21	1010	0	0	0
T22	915	0	0	0
T38	0	2	0	0
T61	1107	0	0	0
T67	0	2	0	0
T102	0	10	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Covered	T2,T36,T37
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	4226	0	0
CgEnOn_A	544414618	4224	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4226	0	0
T2	105976	58	0	0
T3	0	61	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4224	0	0
T2	105976	58	0	0
T3	0	61	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Covered	T2,T37,T3
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	4150	0	0
CgEnOn_A	544414618	4148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4150	0	0
T2	105976	59	0	0
T3	0	62	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T41	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4148	0	0
T2	105976	59	0	0
T3	0	62	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T41	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Covered	T2,T36,T37
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	4148	0	0
CgEnOn_A	544414618	4146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4148	0	0
T2	105976	59	0	0
T3	0	62	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	2	0	0
T37	0	5	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4146	0	0
T2	105976	59	0	0
T3	0	62	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	2	0	0
T37	0	5	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T17
1	0	Covered	T2,T36,T37
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544414618	4143	0	0
CgEnOn_A	544414618	4141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4143	0	0
T2	105976	54	0	0
T3	0	67	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	1	0	0
T37	0	5	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544414618	4141	0	0
T2	105976	54	0	0
T3	0	67	0	0
T5	1502	4	0	0
T6	5871	0	0	0
T17	3422	4	0	0
T18	19053	0	0	0
T19	5991	0	0	0
T20	7369	0	0	0
T21	2104	0	0	0
T22	1907	0	0	0
T36	0	1	0	0
T37	0	5	0	0
T38	0	1	0	0
T61	2305	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T168	0	3	0	0