Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	997422	0	0
SrcPulseCheck_M	2147483647	992950	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	997422
T1	2147913	8564
T2	0	9263
T3	0	242
T4	29354	40
T5	115257	50
T6	284642	188
T12	0	2119
T13	0	3234
T14	0	8124
T19	15031	0
T20	7966	0
T21	24157	0
T22	18246	0
T23	8810	0
T24	10380	0
T25	7725	0
T33	0	166
T34	0	208
T35	0	38
T36	0	100
T56	12594	3
T57	16119	1
T58	8013	4
T59	10052	1
T60	2989	1
T62	4059	1
T64	7615	0
T117	13255	2
T118	4801	1
T119	5283	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	992950
T1	1092468	8567
T2	0	9141
T3	0	242
T4	33460	40
T5	63894	50
T6	101238	188
T12	0	2119
T13	0	3234
T14	0	8127
T19	8937	0
T20	4796	0
T21	6861	0
T22	5913	0
T23	3707	0
T24	5451	0
T25	792	0
T33	0	166
T34	0	208
T35	0	38
T36	0	100
T56	23028	3
T57	6729	1
T58	13309	4
T59	79767	1
T60	5491	1
T62	7520	1
T64	16022	0
T117	24572	2
T118	3366	1
T119	4450	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	566178526	26577	0	0
SrcPulseCheck_M	177521995	26577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	566178526	26577
T1	295010	428
T2	0	480
T3	0	22
T4	25042	8
T5	28469	10
T6	66206	12
T19	3145	0
T20	1687	0
T21	6126	0
T22	4549	0
T23	2107	0
T24	2295	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	26577
T1	338801	428
T2	0	480
T3	0	22
T4	12522	8
T5	27579	10
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	566178526	32213	0	0
SrcPulseCheck_M	177521995	32225	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	566178526	32213
T1	295010	442
T2	0	492
T3	0	22
T4	25042	16
T5	28469	20
T6	66206	12
T19	3145	0
T20	1687	0
T21	6126	0
T22	4549	0
T23	2107	0
T24	2295	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	32225
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	32199	0	0
SrcPulseCheck_M	566178526	32218	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	32199
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	566178526	32218
T1	295010	442
T2	0	492
T3	0	22
T4	25042	16
T5	28469	20
T6	66206	12
T19	3145	0
T20	1687	0
T21	6126	0
T22	4549	0
T23	2107	0
T24	2295	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	282413476	26577	0	0
SrcPulseCheck_M	177521995	26577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	282413476	26577
T1	146950	428
T2	0	480
T3	0	22
T4	8416	8
T5	8444	10
T6	33050	12
T19	1533	0
T20	790	0
T21	3037	0
T22	2221	0
T23	987	0
T24	1101	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	26577
T1	338801	428
T2	0	480
T3	0	22
T4	12522	8
T5	27579	10
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	282413476	32236	0	0
SrcPulseCheck_M	177521995	32267	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	282413476	32236
T1	146950	442
T2	0	492
T3	0	22
T4	8416	16
T5	8444	20
T6	33050	12
T19	1533	0
T20	790	0
T21	3037	0
T22	2221	0
T23	987	0
T24	1101	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	32267
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	32233	0	0
SrcPulseCheck_M	282413476	32238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	32233
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	282413476	32238
T1	146950	442
T2	0	492
T3	0	22
T4	8416	16
T5	8444	20
T6	33050	12
T19	1533	0
T20	790	0
T21	3037	0
T22	2221	0
T23	987	0
T24	1101	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	141206072	26577	0	0
SrcPulseCheck_M	177521995	26577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	141206072	26577
T1	734740	428
T2	0	480
T3	0	22
T4	4209	8
T5	4221	10
T6	16525	12
T19	766	0
T20	395	0
T21	1519	0
T22	1111	0
T23	493	0
T24	550	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	26577
T1	338801	428
T2	0	480
T3	0	22
T4	12522	8
T5	27579	10
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	141206072	32189	0	0
SrcPulseCheck_M	177521995	32207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	141206072	32189
T1	734740	442
T2	0	492
T3	0	22
T4	4209	16
T5	4221	20
T6	16525	12
T19	766	0
T20	395	0
T21	1519	0
T22	1111	0
T23	493	0
T24	550	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	32207
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	32183	0	0
SrcPulseCheck_M	141206072	32192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	32183
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141206072	32192
T1	734740	442
T2	0	492
T3	0	22
T4	4209	16
T5	4221	20
T6	16525	12
T19	766	0
T20	395	0
T21	1519	0
T22	1111	0
T23	493	0
T24	550	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	601175708	26577	0	0
SrcPulseCheck_M	177521995	26577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	601175708	26577
T1	338512	428
T2	0	480
T3	0	22
T4	26086	8
T5	29656	10
T6	68967	12
T19	3277	0
T20	1757	0
T21	6381	0
T22	4739	0
T23	2195	0
T24	2391	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	26577
T1	338801	428
T2	0	480
T3	0	22
T4	12522	8
T5	27579	10
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	601175708	32272	0	0
SrcPulseCheck_M	177521995	32289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	601175708	32272
T1	338512	442
T2	0	492
T3	0	22
T4	26086	16
T5	29656	20
T6	68967	12
T19	3277	0
T20	1757	0
T21	6381	0
T22	4739	0
T23	2195	0
T24	2391	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	32289
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	32256	0	0
SrcPulseCheck_M	601175708	32278	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	32256
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	601175708	32278
T1	338512	442
T2	0	492
T3	0	22
T4	26086	16
T5	29656	20
T6	68967	12
T19	3277	0
T20	1757	0
T21	6381	0
T22	4739	0
T23	2195	0
T24	2391	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	288655722	26148	0	0
SrcPulseCheck_M	177521995	26577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	288655722	26148
T1	159032	428
T2	0	480
T3	0	22
T4	12522	4
T5	14235	5
T6	33105	12
T19	1573	0
T20	844	0
T21	3063	0
T22	2274	0
T23	1054	0
T24	1148	0
T33	0	6
T34	0	8
T35	0	2
T36	0	19

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	26577
T1	338801	428
T2	0	480
T3	0	22
T4	12522	8
T5	27579	10
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	20

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	288655722	32129	0	0
SrcPulseCheck_M	177521995	32265	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	288655722	32129
T1	159032	442
T2	0	492
T3	0	22
T4	12522	12
T5	14235	16
T6	33105	12
T19	1573	0
T20	844	0
T21	3063	0
T22	2274	0
T23	1054	0
T24	1148	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	177521995	32265
T1	338801	442
T2	0	492
T3	0	22
T4	12522	16
T5	27579	20
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T6
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	31994	0	0
SrcPulseCheck_M	288655722	32159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	31994
T1	338801	442
T2	0	492
T3	0	22
T4	12522	12
T5	27579	16
T6	33794	12
T19	3244	0
T20	1757	0
T21	1020	0
T22	1184	0
T23	1054	0
T24	1841	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	288655722	32159
T1	159032	442
T2	0	492
T3	0	22
T4	12522	13
T5	14235	16
T6	33105	12
T19	1573	0
T20	844	0
T21	3063	0
T22	2274	0
T23	1054	0
T24	1148	0
T33	0	6
T34	0	8
T35	0	2
T36	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T57
1	0	Covered	T54,T55,T57
1	1	Covered	T120,T121,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T57
1	0	Covered	T120,T121,T122
1	1	Covered	T54,T55,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	41	0	0
SrcPulseCheck_M	566178526	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	41
T54	14496	1
T55	7097	2
T57	16119	2
T59	10052	1
T60	2989	1
T63	14375	1
T64	7615	2
T117	13255	2
T120	6391	3
T123	8864	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	566178526	41
T54	30251	1
T55	7097	2
T57	15474	2
T59	160839	1
T60	11956	1
T63	14375	1
T64	33227	2
T117	50898	2
T120	22723	3
T123	9780	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T57
1	0	Covered	T54,T55,T57
1	1	Covered	T60,T117,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T57
1	0	Covered	T60,T117,T121
1	1	Covered	T54,T55,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	41	0	0
SrcPulseCheck_M	566178526	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	41
T54	14496	1
T55	7097	1
T57	16119	2
T59	10052	1
T60	2989	3
T63	14375	1
T64	7615	2
T117	13255	3
T120	6391	2
T123	8864	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	566178526	41
T54	30251	1
T55	7097	1
T57	15474	2
T59	160839	1
T60	11956	3
T63	14375	1
T64	33227	2
T117	50898	3
T120	22723	2
T123	9780	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T56,T57,T59
1	0	Covered	T56,T57,T59
1	1	Covered	T58,T64,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T56,T57,T59
1	0	Covered	T58,T64,T124
1	1	Covered	T56,T57,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	41	0	0
SrcPulseCheck_M	282413476	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	41
T56	12594	3
T57	16119	1
T58	8013	4
T59	10052	1
T60	2989	1
T62	4059	1
T64	7615	3
T117	13255	2
T118	4801	1
T119	5283	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	282413476	41
T56	23028	3
T57	6729	1
T58	13309	4
T59	79767	1
T60	5491	1
T62	7520	1
T64	16022	3
T117	24572	2
T118	3366	1
T119	4450	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T59,T58
1	0	Covered	T57,T59,T58
1	1	Covered	T58,T64,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T59,T58
1	0	Covered	T58,T64,T122
1	1	Covered	T57,T59,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	31	0	0
SrcPulseCheck_M	282413476	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	31
T57	16119	2
T58	8013	4
T59	10052	2
T60	2989	1
T62	4059	1
T64	7615	2
T117	13255	1
T119	5283	1
T121	5981	1
T124	3985	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	282413476	31
T57	6729	2
T58	13309	4
T59	79767	2
T60	5491	1
T62	7520	1
T64	16022	2
T117	24572	1
T119	4450	1
T121	2407	1
T124	5923	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T55,T56
1	1	Covered	T55,T59,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T55,T59,T125
1	1	Covered	T54,T55,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	42	0	0
SrcPulseCheck_M	141206072	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	42
T54	14496	1
T55	7097	3
T56	12594	1
T58	8013	2
T59	10052	2
T60	2989	1
T64	7615	3
T117	13255	1
T120	6391	1
T124	3985	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141206072	42
T54	7104	1
T55	1562	3
T56	11515	1
T58	6656	2
T59	39884	2
T60	2743	1
T64	8012	3
T117	12287	1
T120	5342	1
T124	2960	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T55,T56
1	1	Covered	T60,T120,T126

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T60,T120,T126
1	1	Covered	T54,T55,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	37	0	0
SrcPulseCheck_M	141206072	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	37
T54	14496	1
T55	7097	2
T56	12594	1
T58	8013	2
T59	10052	1
T60	2989	2
T62	4059	1
T64	7615	3
T120	6391	2
T122	12371	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141206072	37
T54	7104	1
T55	1562	2
T56	11515	1
T58	6656	2
T59	39884	1
T60	2743	2
T62	3759	1
T64	8012	3
T120	5342	2
T122	2667	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T59,T58
1	0	Covered	T54,T59,T58
1	1	Covered	T121,T125,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T59,T58
1	0	Covered	T121,T125,T127
1	1	Covered	T54,T59,T58

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	32	0	0
SrcPulseCheck_M	601175708	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	32
T54	14496	2
T58	8013	1
T59	10052	1
T61	7984	1
T63	14375	2
T119	5283	1
T120	6391	2
T121	5981	2
T124	3985	1
T128	8131	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	601175708	32
T54	31513	2
T58	29677	1
T59	167547	1
T61	8317	1
T63	14975	2
T119	10565	1
T120	23671	2
T121	5981	2
T124	13284	1
T128	32523	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T59,T58
1	0	Covered	T54,T59,T58
1	1	Covered	T124,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T59,T58
1	0	Covered	T124,T125
1	1	Covered	T54,T59,T58

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	33	0	0
SrcPulseCheck_M	601175708	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	33
T54	14496	2
T58	8013	2
T59	10052	1
T61	7984	1
T117	13255	3
T120	6391	2
T121	5981	1
T124	3985	2
T125	3563	2
T128	8131	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	601175708	33
T54	31513	2
T58	29677	2
T59	167547	1
T61	8317	1
T117	53020	3
T120	23671	2
T121	5981	1
T124	13284	2
T125	29692	2
T128	32523	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T63
1	0	Covered	T54,T55,T63
1	1	Covered	T64,T129,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T63
1	0	Covered	T64,T129,T130
1	1	Covered	T54,T55,T63

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	33	0	0
SrcPulseCheck_M	288655722	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	33
T54	14496	1
T55	7097	2
T61	7984	1
T63	14375	2
T64	7615	5
T118	4801	1
T120	6391	1
T122	12371	1
T123	8864	1
T128	8131	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	288655722	33
T54	15126	1
T55	3549	2
T61	3992	1
T63	7188	2
T64	16614	5
T118	3841	1
T120	11362	1
T122	6251	1
T123	4890	1
T128	15611	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T63
1	0	Covered	T54,T55,T63
1	1	Covered	T54,T64,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T63
1	0	Covered	T54,T64,T131
1	1	Covered	T54,T55,T63

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	177521995	35	0	0
SrcPulseCheck_M	288655722	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	177521995	35
T54	14496	3
T55	7097	2
T61	7984	1
T63	14375	2
T64	7615	3
T119	5283	1
T120	6391	2
T123	8864	1
T128	8131	1
T132	7431	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	288655722	35
T54	15126	3
T55	3549	2
T61	3992	1
T63	7188	2
T64	16614	3
T119	5071	1
T120	11362	2
T123	4890	1
T128	15611	1
T132	3566	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	563293994	102245	0	0
SrcPulseCheck_M	21706060	101154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	563293994	102245
T1	295010	1659
T2	0	1834
T3	0	44
T5	28469	0
T6	66206	38
T12	0	524
T13	0	806
T14	0	2088
T19	3145	0
T20	1687	0
T21	6126	0
T22	4549	0
T23	2107	0
T24	2295	0
T25	2718	0
T33	0	37
T34	0	40
T35	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21706060	101154
T1	66823	1660
T2	0	1799
T3	0	44
T5	73	0
T6	150	38
T12	0	524
T13	0	806
T14	0	2089
T19	229	0
T20	123	0
T21	446	0
T22	331	0
T23	153	0
T24	167	0
T25	198	0
T33	0	37
T34	0	40
T35	0	5

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	281016201	101250	0	0
SrcPulseCheck_M	21706060	100161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	281016201	101250
T1	146950	1659
T2	0	1825
T3	0	44
T5	8444	0
T6	33050	38
T12	0	524
T13	0	801
T14	0	1958
T19	1533	0
T20	790	0
T21	3037	0
T22	2221	0
T23	987	0
T24	1101	0
T25	1450	0
T33	0	37
T34	0	40
T35	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21706060	100161
T1	66823	1660
T2	0	1790
T3	0	44
T5	73	0
T6	150	38
T12	0	524
T13	0	801
T14	0	1959
T19	229	0
T20	123	0
T21	446	0
T22	331	0
T23	153	0
T24	167	0
T25	198	0
T33	0	37
T34	0	40
T35	0	5

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	140507411	99770	0	0
SrcPulseCheck_M	21706060	98687	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	140507411	99770
T1	734740	1659
T2	0	1816
T3	0	44
T5	4221	0
T6	16525	38
T12	0	524
T13	0	789
T14	0	1872
T19	766	0
T20	395	0
T21	1519	0
T22	1111	0
T23	493	0
T24	550	0
T25	725	0
T33	0	37
T34	0	40
T35	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21706060	98687
T1	66823	1660
T2	0	1781
T3	0	44
T5	73	0
T6	150	38
T12	0	524
T13	0	789
T14	0	1873
T19	229	0
T20	123	0
T21	446	0
T22	331	0
T23	153	0
T24	167	0
T25	198	0
T33	0	37
T34	0	40
T35	0	5

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	598170860	120399	0	0
SrcPulseCheck_M	21355865	118879	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	598170860	120399
T1	338512	2275
T2	0	2324
T3	0	44
T5	29656	0
T6	68967	38
T12	0	547
T13	0	838
T14	0	2206
T19	3277	0
T20	1757	0
T21	6381	0
T22	4739	0
T23	2195	0
T24	2391	0
T25	2832	0
T33	0	37
T34	0	64
T35	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21355865	118879
T1	67447	2275
T2	0	2307
T3	0	44
T5	73	0
T6	150	38
T12	0	547
T13	0	838
T14	0	2206
T19	229	0
T20	123	0
T21	446	0
T22	331	0
T23	153	0
T24	167	0
T25	198	0
T33	0	37
T34	0	64
T35	0	17

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	287213419	119032	0	0
SrcPulseCheck_M	21452025	118480	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	287213419	119032
T1	159032	2132
T2	0	2315
T3	0	44
T5	14235	0
T6	33105	38
T12	0	557
T13	0	840
T14	0	2015
T19	1573	0
T20	844	0
T21	3063	0
T22	2274	0
T23	1054	0
T24	1148	0
T25	1359	0
T33	0	37
T34	0	52
T35	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21452025	118480
T1	67303	2133
T2	0	2315
T3	0	44
T5	73	0
T6	150	38
T12	0	557
T13	0	840
T14	0	2015
T19	229	0
T20	123	0
T21	446	0
T22	331	0
T23	153	0
T24	167	0
T25	198	0
T33	0	37
T34	0	52
T35	0	17

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb