Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1775219950	1468036	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1775219950	293342	0	0
SrcBusyKnown_A	1775219950	1750144140	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1775219950	1468036	0	0
T1	3388010	35242	0	0
T2	0	25671	0	0
T3	0	1565	0	0
T4	125220	584	0	0
T5	275790	1163	0	0
T6	337940	640	0	0
T19	32440	0	0	0
T20	17570	0	0	0
T21	10200	0	0	0
T22	11840	0	0	0
T23	10540	0	0	0
T24	18410	0	0	0
T33	0	311	0	0
T34	0	545	0	0
T35	0	160	0	0
T36	0	966	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3348488	3324098	0	0
T4	152550	18896	0	0
T7	80902	80234	0	0
T8	34030	33374	0	0
T9	29222	27934	0	0
T26	8942	8450	0	0
T27	38772	37432	0	0
T28	10410	8914	0	0
T29	14538	14052	0	0
T30	118708	118306	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1775219950	293342	0	0
T1	3388010	4350	0	0
T2	0	4860	0	0
T3	0	220	0	0
T4	125220	112	0	0
T5	275790	141	0	0
T6	337940	120	0	0
T19	32440	0	0	0
T20	17570	0	0	0
T21	10200	0	0	0
T22	11840	0	0	0
T23	10540	0	0	0
T24	18410	0	0	0
T33	0	60	0	0
T34	0	80	0	0
T35	0	20	0	0
T36	0	295	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1775219950	1750144140	0	0
T1	3388010	3355360	0	0
T4	125220	14350	0	0
T7	30730	30460	0	0
T8	12260	12010	0	0
T9	22740	21610	0	0
T26	14920	14100	0	0
T27	15190	14600	0	0
T28	16060	13480	0	0
T29	11520	11110	0	0
T30	13150	13110	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	94070	0	0
DstReqKnown_A	566178526	561934471	0	0
SrcAckBusyChk_A	177521995	26577	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	94070	0	0
T1	338801	2169	0	0
T2	0	1772	0	0
T3	0	99	0	0
T4	12522	29	0	0
T5	27579	52	0	0
T6	33794	44	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	21	0	0
T34	0	38	0	0
T35	0	10	0	0
T36	0	47	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566178526	561934471	0	0
T1	295010	292226	0	0
T4	25042	2870	0	0
T7	12294	12187	0	0
T8	4935	4814	0	0
T9	4367	4150	0	0
T26	1373	1293	0	0
T27	5838	5607	0	0
T28	1606	1348	0	0
T29	2214	2135	0	0
T30	18037	17970	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	26577	0	0
T1	338801	428	0	0
T2	0	480	0	0
T3	0	22	0	0
T4	12522	8	0	0
T5	27579	10	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	132745	0	0
DstReqKnown_A	282413476	281330821	0	0
SrcAckBusyChk_A	177521995	26577	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	132745	0	0
T1	338801	3484	0	0
T2	0	2545	0	0
T3	0	160	0	0
T4	12522	42	0	0
T5	27579	81	0	0
T6	33794	65	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	30	0	0
T34	0	53	0	0
T35	0	16	0	0
T36	0	65	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282413476	281330821	0	0
T1	146950	146197	0	0
T4	8416	1435	0	0
T7	6135	6094	0	0
T8	2421	2407	0	0
T9	2343	2281	0	0
T26	674	646	0	0
T27	3034	2979	0	0
T28	749	687	0	0
T29	1095	1068	0	0
T30	9006	8985	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	26577	0	0
T1	338801	428	0	0
T2	0	480	0	0
T3	0	22	0	0
T4	12522	8	0	0
T5	27579	10	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	210551	0	0
DstReqKnown_A	141206072	140664855	0	0
SrcAckBusyChk_A	177521995	26577	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	210551	0	0
T1	338801	6112	0	0
T2	0	4079	0	0
T3	0	273	0	0
T4	12522	66	0	0
T5	27579	138	0	0
T6	33794	101	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	47	0	0
T34	0	90	0	0
T35	0	29	0	0
T36	0	92	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141206072	140664855	0	0
T1	734740	730977	0	0
T4	4209	719	0	0
T7	3067	3046	0	0
T8	1211	1204	0	0
T9	1170	1139	0	0
T26	337	323	0	0
T27	1515	1487	0	0
T28	374	343	0	0
T29	547	533	0	0
T30	4503	4492	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	26577	0	0
T1	338801	428	0	0
T2	0	480	0	0
T3	0	22	0	0
T4	12522	8	0	0
T5	27579	10	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	91822	0	0
DstReqKnown_A	601175708	596693766	0	0
SrcAckBusyChk_A	177521995	26577	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	91822	0	0
T1	338801	2119	0	0
T2	0	1715	0	0
T3	0	99	0	0
T4	12522	29	0	0
T5	27579	51	0	0
T6	33794	44	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	20	0	0
T34	0	39	0	0
T35	0	10	0	0
T36	0	47	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601175708	596693766	0	0
T1	338512	335181	0	0
T4	26086	2989	0	0
T7	12808	12696	0	0
T8	5745	5619	0	0
T9	4548	4322	0	0
T26	1425	1341	0	0
T27	6081	5840	0	0
T28	1673	1404	0	0
T29	2307	2223	0	0
T30	18789	18720	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	26577	0	0
T1	338801	428	0	0
T2	0	480	0	0
T3	0	22	0	0
T4	12522	8	0	0
T5	27579	10	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	130713	0	0
DstReqKnown_A	288655722	286497396	0	0
SrcAckBusyChk_A	177521995	26135	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	130713	0	0
T1	338801	3480	0	0
T2	0	2543	0	0
T3	0	157	0	0
T4	12522	28	0	0
T5	27579	50	0	0
T6	33794	66	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	36	0	0
T34	0	54	0	0
T35	0	16	0	0
T36	0	61	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288655722	286497396	0	0
T1	159032	157468	0	0
T4	12522	1435	0	0
T7	6147	6094	0	0
T8	2703	2643	0	0
T9	2183	2075	0	0
T26	662	622	0	0
T27	2918	2803	0	0
T28	803	675	0	0
T29	1106	1067	0	0
T30	9019	8986	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	26135	0	0
T1	338801	428	0	0
T2	0	480	0	0
T3	0	22	0	0
T4	12522	4	0	0
T5	27579	5	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	15	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	114477	0	0
DstReqKnown_A	566178526	561934471	0	0
SrcAckBusyChk_A	177521995	32204	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	114477	0	0
T1	338801	2250	0	0
T2	0	1803	0	0
T3	0	95	0	0
T4	12522	55	0	0
T5	27579	102	0	0
T6	33794	46	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	21	0	0
T34	0	37	0	0
T35	0	10	0	0
T36	0	98	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	566178526	561934471	0	0
T1	295010	292226	0	0
T4	25042	2870	0	0
T7	12294	12187	0	0
T8	4935	4814	0	0
T9	4367	4150	0	0
T26	1373	1293	0	0
T27	5838	5607	0	0
T28	1606	1348	0	0
T29	2214	2135	0	0
T30	18037	17970	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	32204	0	0
T1	338801	442	0	0
T2	0	492	0	0
T3	0	22	0	0
T4	12522	16	0	0
T5	27579	20	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	161791	0	0
DstReqKnown_A	282413476	281330821	0	0
SrcAckBusyChk_A	177521995	32236	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	161791	0	0
T1	338801	3586	0	0
T2	0	2624	0	0
T3	0	153	0	0
T4	12522	78	0	0
T5	27579	160	0	0
T6	33794	64	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	30	0	0
T34	0	54	0	0
T35	0	17	0	0
T36	0	133	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282413476	281330821	0	0
T1	146950	146197	0	0
T4	8416	1435	0	0
T7	6135	6094	0	0
T8	2421	2407	0	0
T9	2343	2281	0	0
T26	674	646	0	0
T27	3034	2979	0	0
T28	749	687	0	0
T29	1095	1068	0	0
T30	9006	8985	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	32236	0	0
T1	338801	442	0	0
T2	0	492	0	0
T3	0	22	0	0
T4	12522	16	0	0
T5	27579	20	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	257758	0	0
DstReqKnown_A	141206072	140664855	0	0
SrcAckBusyChk_A	177521995	32185	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	257758	0	0
T1	338801	6246	0	0
T2	0	4227	0	0
T3	0	279	0	0
T4	12522	123	0	0
T5	27579	283	0	0
T6	33794	102	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	49	0	0
T34	0	89	0	0
T35	0	26	0	0
T36	0	189	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141206072	140664855	0	0
T1	734740	730977	0	0
T4	4209	719	0	0
T7	3067	3046	0	0
T8	1211	1204	0	0
T9	1170	1139	0	0
T26	337	323	0	0
T27	1515	1487	0	0
T28	374	343	0	0
T29	547	533	0	0
T30	4503	4492	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	32185	0	0
T1	338801	442	0	0
T2	0	492	0	0
T3	0	22	0	0
T4	12522	16	0	0
T5	27579	20	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	112124	0	0
DstReqKnown_A	601175708	596693766	0	0
SrcAckBusyChk_A	177521995	32261	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	112124	0	0
T1	338801	2193	0	0
T2	0	1765	0	0
T3	0	97	0	0
T4	12522	54	0	0
T5	27579	102	0	0
T6	33794	44	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	21	0	0
T34	0	37	0	0
T35	0	10	0	0
T36	0	98	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601175708	596693766	0	0
T1	338512	335181	0	0
T4	26086	2989	0	0
T7	12808	12696	0	0
T8	5745	5619	0	0
T9	4548	4322	0	0
T26	1425	1341	0	0
T27	6081	5840	0	0
T28	1673	1404	0	0
T29	2307	2223	0	0
T30	18789	18720	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	32261	0	0
T1	338801	442	0	0
T2	0	492	0	0
T3	0	22	0	0
T4	12522	16	0	0
T5	27579	20	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T1,T6
0	0	1	Covered	T4,T1,T6
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	177521995	161985	0	0
DstReqKnown_A	288655722	286497396	0	0
SrcAckBusyChk_A	177521995	32013	0	0
SrcBusyKnown_A	177521995	175014414	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	161985	0	0
T1	338801	3603	0	0
T2	0	2598	0	0
T3	0	153	0	0
T4	12522	80	0	0
T5	27579	144	0	0
T6	33794	64	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	36	0	0
T34	0	54	0	0
T35	0	16	0	0
T36	0	136	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288655722	286497396	0	0
T1	159032	157468	0	0
T4	12522	1435	0	0
T7	6147	6094	0	0
T8	2703	2643	0	0
T9	2183	2075	0	0
T26	662	622	0	0
T27	2918	2803	0	0
T28	803	675	0	0
T29	1106	1067	0	0
T30	9019	8986	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	32013	0	0
T1	338801	442	0	0
T2	0	492	0	0
T3	0	22	0	0
T4	12522	12	0	0
T5	27579	16	0	0
T6	33794	12	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T33	0	6	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	175014414	0	0
T1	338801	335536	0	0
T4	12522	1435	0	0
T7	3073	3046	0	0
T8	1226	1201	0	0
T9	2274	2161	0	0
T26	1492	1410	0	0
T27	1519	1460	0	0
T28	1606	1348	0	0
T29	1152	1111	0	0
T30	1315	1311	0	0