Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_step_down_req_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_main_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_usb_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_usb_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_io_step_down_req_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

---

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22512	22512	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	1014543300	998391426	0	14472
gen_flops.gen_stable_chks.OutputDelay_A	2147483647	2147483647	0	16884
gen_flops.gen_stable_chks.OutputIfUnstable_A	2147483647	209271	0	0
gen_no_flops.OutputDelay_A	2147483647	2147483647	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512	22512	0	0
T1	28	28	0	0
T2	28	28	0	0
T4	28	28	0	0
T5	28	28	0	0
T14	28	28	0	0
T15	28	28	0	0
T16	28	28	0	0
T17	28	28	0	0
T18	28	28	0	0
T19	28	28	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12991195	12906872	0	0
T2	13841919	13834185	0	0
T4	261414	259088	0	0
T5	80333	78825	0	0
T14	37922	32200	0	0
T15	66902	64996	0	0
T16	65891	62165	0	0
T17	47465	42674	0	0
T18	42519	39935	0	0
T19	42704	38529	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014543300	998391426	0	14472
T1	2970366	2949858	0	18
T2	1401042	1400112	0	18
T4	42954	42522	0	18
T5	7722	7530	0	18
T14	8646	7218	0	18
T15	6024	5814	0	18
T16	15084	14136	0	18
T17	10860	9666	0	18
T18	6510	6048	0	18
T19	9582	8520	0	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	16884
T1	3472931	3448437	0	21
T2	4796848	4794000	0	21
T4	81017	80160	0	21
T5	27140	26506	0	21
T14	10178	8492	0	21
T15	23659	22879	0	21
T16	17498	16399	0	21
T17	12687	11292	0	21
T18	13374	12441	0	21
T19	11532	10255	0	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	209271	0	0
T1	3472931	2735	0	0
T2	4796848	1579	0	0
T3	0	1115	0	0
T4	73858	4	0	0
T5	25853	79	0	0
T8	0	260	0	0
T9	0	579	0	0
T14	10178	12	0	0
T15	23659	40	0	0
T16	17498	214	0	0
T17	12687	51	0	0
T18	13374	58	0	0
T19	11532	16	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T80	0	26	0	0
T81	0	35	0	0
T120	0	3	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6547898	6508537	0	0
T2	7644029	7640047	0	0
T4	137443	136367	0	0
T5	45471	44750	0	0
T14	19098	16451	0	0
T15	37219	36264	0	0
T16	33309	31591	0	0
T17	23918	21677	0	0
T18	22635	21407	0	0
T19	21590	19715	0	0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

---

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	534662876	530204256	0	0
gen_flops.gen_stable_chks.OutputDelay_A	534662876	530197038	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	534662876	29243	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	530204256	0	0
T1	467989	464575	0	0
T2	818966	818802	0	0
T4	8263	8129	0	0
T5	4754	4647	0	0
T14	1412	1181	0	0
T15	4191	4056	0	0
T16	2414	2266	0	0
T17	1755	1565	0	0
T18	2168	2020	0	0
T19	1614	1438	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	530197038	0	2412
T1	467989	464571	0	3
T2	818966	818800	0	3
T4	8263	8126	0	3
T5	4754	4644	0	3
T14	1412	1178	0	3
T15	4191	4053	0	3
T16	2414	2263	0	3
T17	1755	1562	0	3
T18	2168	2017	0	3
T19	1614	1435	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	29243	0	0
T1	467989	465	0	0
T2	818966	146	0	0
T3	0	473	0	0
T4	8263	0	0	0
T5	4754	20	0	0
T8	0	102	0	0
T9	0	247	0	0
T14	1412	0	0	0
T15	4191	0	0	0
T16	2414	42	0	0
T17	1755	21	0	0
T18	2168	0	0	0
T19	1614	0	0	0
T80	0	11	0	0
T81	0	16	0	0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T1,T16,T2

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T1,T16,T2

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T1,T16,T2

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T1,T16,T2

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T2
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T2
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T2
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T2
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_stable_chks.OutputDelay_A	169090550	166398571	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	169090550	18127	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	18127	0	0
T1	495061	289	0	0
T2	233507	95	0	0
T3	0	324	0	0
T8	0	71	0	0
T9	0	154	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	56	0	0
T17	1810	6	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T80	0	7	0	0
T81	0	8	0	0
T120	0	3	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T1,T16

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T16
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_stable_chks.OutputDelay_A	169090550	166398571	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	169090550	20614	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	20614	0	0
T1	495061	359	0	0
T2	233507	111	0	0
T3	0	318	0	0
T4	7159	0	0	0
T5	1287	19	0	0
T8	0	87	0	0
T9	0	178	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	58	0	0
T17	1810	8	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T80	0	8	0	0
T81	0	11	0	0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	565563173	0	0
gen_no_flops.OutputDelay_A	567873163	565563173	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	565563173	0	0
T1	503705	501802	0	0
T2	877717	877273	0	0
T4	14609	14568	0	0
T5	4953	4912	0	0
T14	1471	1359	0	0
T15	4365	4282	0	0
T16	2514	2445	0	0
T17	1828	1716	0	0
T18	2259	2190	0	0
T19	1681	1641	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	565563173	0	0
T1	503705	501802	0	0
T2	877717	877273	0	0
T4	14609	14568	0	0
T5	4953	4912	0	0
T14	1471	1359	0	0
T15	4365	4282	0	0
T16	2514	2445	0	0
T17	1828	1716	0	0
T18	2259	2190	0	0
T19	1681	1641	0	0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	534662876	532473939	0	0
gen_no_flops.OutputDelay_A	534662876	532473939	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	532473939	0	0
T1	467989	466163	0	0
T2	818966	818924	0	0
T4	8263	8225	0	0
T5	4754	4715	0	0
T14	1412	1305	0	0
T15	4191	4111	0	0
T16	2414	2348	0	0
T17	1755	1647	0	0
T18	2168	2102	0	0
T19	1614	1575	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	532473939	0	0
T1	467989	466163	0	0
T2	818966	818924	0	0
T4	8263	8225	0	0
T5	4754	4715	0	0
T14	1412	1305	0	0
T15	4191	4111	0	0
T16	2414	2348	0	0
T17	1755	1647	0	0
T18	2168	2102	0	0
T19	1614	1575	0	0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	266546921	266546921	0	0
gen_no_flops.OutputDelay_A	266546921	266546921	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	266546921	0	0
T1	233209	233209	0	0
T2	409609	409609	0	0
T4	4113	4113	0	0
T5	3902	3902	0	0
T14	653	653	0	0
T15	2056	2056	0	0
T16	1356	1356	0	0
T17	859	859	0	0
T18	1051	1051	0	0
T19	788	788	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	266546921	0	0
T1	233209	233209	0	0
T2	409609	409609	0	0
T4	4113	4113	0	0
T5	3902	3902	0	0
T14	653	653	0	0
T15	2056	2056	0	0
T16	1356	1356	0	0
T17	859	859	0	0
T18	1051	1051	0	0
T19	788	788	0	0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	133272841	133272841	0	0
gen_no_flops.OutputDelay_A	133272841	133272841	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	133272841	0	0
T1	116603	116603	0	0
T2	204804	204804	0	0
T4	2056	2056	0	0
T5	1951	1951	0	0
T14	326	326	0	0
T15	1028	1028	0	0
T16	678	678	0	0
T17	427	427	0	0
T18	526	526	0	0
T19	394	394	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	133272841	0	0
T1	116603	116603	0	0
T2	204804	204804	0	0
T4	2056	2056	0	0
T5	1951	1951	0	0
T14	326	326	0	0
T15	1028	1028	0	0
T16	678	678	0	0
T17	427	427	0	0
T18	526	526	0	0
T19	394	394	0	0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	272734796	271622217	0	0
gen_no_flops.OutputDelay_A	272734796	271622217	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	271622217	0	0
T1	241206	240292	0	0
T2	421023	420809	0	0
T4	7012	6993	0	0
T5	2377	2358	0	0
T14	706	652	0	0
T15	2095	2055	0	0
T16	1207	1174	0	0
T17	877	824	0	0
T18	1085	1052	0	0
T19	807	787	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	271622217	0	0
T1	241206	240292	0	0
T2	421023	420809	0	0
T4	7012	6993	0	0
T5	2377	2358	0	0
T14	706	652	0	0
T15	2095	2055	0	0
T16	1207	1174	0	0
T17	877	824	0	0
T18	1085	1052	0	0
T19	807	787	0	0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	169090550	166398571	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166398571	0	2412
T1	495061	491643	0	3
T2	233507	233352	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	2356	0	3
T17	1810	1611	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	169090550	166405899	0	0
gen_no_flops.OutputDelay_A	169090550	166405899	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

---

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_flops.gen_stable_chks.OutputDelay_A	567873163	563142775	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	567873163	35097	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563142775	0	2412
T1	503705	500145	0	3
T2	877717	877124	0	3
T4	14609	14465	0	3
T5	4953	4838	0	3
T14	1471	1227	0	3
T15	4365	4222	0	3
T16	2514	2356	0	3
T17	1828	1627	0	3
T18	2259	2102	0	3
T19	1681	1495	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	35097	0	0
T1	503705	410	0	0
T2	877717	285	0	0
T4	14609	1	0	0
T5	4953	7	0	0
T14	1471	3	0	0
T15	4365	10	0	0
T16	2514	9	0	0
T17	1828	6	0	0
T18	2259	17	0	0
T19	1681	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_no_flops.OutputDelay_A	567873163	563150019	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

---

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_flops.gen_stable_chks.OutputDelay_A	567873163	563142775	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	567873163	35594	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563142775	0	2412
T1	503705	500145	0	3
T2	877717	877124	0	3
T4	14609	14465	0	3
T5	4953	4838	0	3
T14	1471	1227	0	3
T15	4365	4222	0	3
T16	2514	2356	0	3
T17	1828	1627	0	3
T18	2259	2102	0	3
T19	1681	1495	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	35594	0	0
T1	503705	409	0	0
T2	877717	307	0	0
T4	14609	1	0	0
T5	4953	13	0	0
T14	1471	3	0	0
T15	4365	12	0	0
T16	2514	19	0	0
T17	1828	2	0	0
T18	2259	11	0	0
T19	1681	1	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_no_flops.OutputDelay_A	567873163	563150019	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

---

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_flops.gen_stable_chks.OutputDelay_A	567873163	563142775	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	567873163	35442	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563142775	0	2412
T1	503705	500145	0	3
T2	877717	877124	0	3
T4	14609	14465	0	3
T5	4953	4838	0	3
T14	1471	1227	0	3
T15	4365	4222	0	3
T16	2514	2356	0	3
T17	1828	1627	0	3
T18	2259	2102	0	3
T19	1681	1495	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	35442	0	0
T1	503705	381	0	0
T2	877717	344	0	0
T4	14609	1	0	0
T5	4953	7	0	0
T14	1471	3	0	0
T15	4365	10	0	0
T16	2514	15	0	0
T17	1828	2	0	0
T18	2259	15	0	0
T19	1681	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_no_flops.OutputDelay_A	567873163	563150019	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T4,T1
1	Covered	T5,T4,T1

---

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T1
0	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_flops.gen_stable_chks.OutputDelay_A	567873163	563142775	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	567873163	35154	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563142775	0	2412
T1	503705	500145	0	3
T2	877717	877124	0	3
T4	14609	14465	0	3
T5	4953	4838	0	3
T14	1471	1227	0	3
T15	4365	4222	0	3
T16	2514	2356	0	3
T17	1828	1627	0	3
T18	2259	2102	0	3
T19	1681	1495	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	35154	0	0
T1	503705	422	0	0
T2	877717	291	0	0
T4	14609	1	0	0
T5	4953	13	0	0
T14	1471	3	0	0
T15	4365	8	0	0
T16	2514	15	0	0
T17	1828	6	0	0
T18	2259	15	0	0
T19	1681	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	567873163	563150019	0	0
gen_no_flops.OutputDelay_A	567873163	563150019	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0