Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_io_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_all_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_byp_req

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6858633	6813626	0	0
T2	10085235	10080088	0	0
T4	156131	154484	0	0
T5	63449	62234	0	0
T14	19995	16904	0	0
T15	49998	48546	0	0
T16	35292	33287	0	0
T17	25088	22578	0	0
T18	27521	25765	0	0
T19	22871	20449	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169090550	166405899	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169090550	166405899	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169090550	166405899	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166405899	0	0
T1	495061	491646	0	0
T2	233507	233354	0	0
T4	7159	7090	0	0
T5	1287	1258	0	0
T14	1441	1206	0	0
T15	1004	972	0	0
T16	2514	2359	0	0
T17	1810	1614	0	0
T18	1085	1011	0	0
T19	1597	1423	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133272841	132705246	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	132705246	0	0
T1	116603	116206	0	0
T2	204804	204773	0	0
T4	2056	2032	0	0
T5	1951	1934	0	0
T14	326	295	0	0
T15	1028	1014	0	0
T16	678	657	0	0
T17	427	406	0	0
T18	526	505	0	0
T19	394	360	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	272734796	270461502	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	270461502	0	0
T1	241206	239498	0	0
T2	421023	420739	0	0
T4	7012	6945	0	0
T5	2377	2324	0	0
T14	706	591	0	0
T15	2095	2028	0	0
T16	1207	1133	0	0
T17	877	783	0	0
T18	1085	1011	0	0
T19	807	719	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	534662876	530204256	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	530204256	0	0
T1	467989	464575	0	0
T2	818966	818802	0	0
T4	8263	8129	0	0
T5	4754	4647	0	0
T14	1412	1181	0	0
T15	4191	4056	0	0
T16	2414	2266	0	0
T17	1755	1565	0	0
T18	2168	2020	0	0
T19	1614	1438	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	266546921	265411605	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	265411605	0	0
T1	233209	232415	0	0
T2	409609	409548	0	0
T4	4113	4065	0	0
T5	3902	3868	0	0
T14	653	591	0	0
T15	2056	2028	0	0
T16	1356	1315	0	0
T17	859	818	0	0
T18	1051	1010	0	0
T19	788	719	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133272841	132705246	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	132705246	0	0
T1	116603	116206	0	0
T2	204804	204773	0	0
T4	2056	2032	0	0
T5	1951	1934	0	0
T14	326	295	0	0
T15	1028	1014	0	0
T16	678	657	0	0
T17	427	406	0	0
T18	526	505	0	0
T19	394	360	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133272841	132705246	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	132705246	0	0
T1	116603	116206	0	0
T2	204804	204773	0	0
T4	2056	2032	0	0
T5	1951	1934	0	0
T14	326	295	0	0
T15	1028	1014	0	0
T16	678	657	0	0
T17	427	406	0	0
T18	526	505	0	0
T19	394	360	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133272841	132705246	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	132705246	0	0
T1	116603	116206	0	0
T2	204804	204773	0	0
T4	2056	2032	0	0
T5	1951	1934	0	0
T14	326	295	0	0
T15	1028	1014	0	0
T16	678	657	0	0
T17	427	406	0	0
T18	526	505	0	0
T19	394	360	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	266546921	265411605	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	265411605	0	0
T1	233209	232415	0	0
T2	409609	409548	0	0
T4	4113	4065	0	0
T5	3902	3868	0	0
T14	653	591	0	0
T15	2056	2028	0	0
T16	1356	1315	0	0
T17	859	818	0	0
T18	1051	1010	0	0
T19	788	719	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	534662876	530204256	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	530204256	0	0
T1	467989	464575	0	0
T2	818966	818802	0	0
T4	8263	8129	0	0
T5	4754	4647	0	0
T14	1412	1181	0	0
T15	4191	4056	0	0
T16	2414	2266	0	0
T17	1755	1565	0	0
T18	2168	2020	0	0
T19	1614	1438	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	272734796	270461502	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	270461502	0	0
T1	241206	239498	0	0
T2	421023	420739	0	0
T4	7012	6945	0	0
T5	2377	2324	0	0
T14	706	591	0	0
T15	2095	2028	0	0
T16	1207	1133	0	0
T17	877	783	0	0
T18	1085	1011	0	0
T19	807	719	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	567873163	563150019	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	563150019	0	0
T1	503705	500148	0	0
T2	877717	877126	0	0
T4	14609	14468	0	0
T5	4953	4841	0	0
T14	1471	1230	0	0
T15	4365	4225	0	0
T16	2514	2359	0	0
T17	1828	1630	0	0
T18	2259	2105	0	0
T19	1681	1498	0	0