SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1608 | 1608 | 0 | 0 |
OutputsKnown_A | 338181100 | 332811798 | 0 | 0 |
gen_flops.OutputDelay_A | 338181100 | 332797142 | 0 | 4824 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1608 | 1608 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T14 | 2 | 2 | 0 | 0 |
T15 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 338181100 | 332811798 | 0 | 0 |
T1 | 990122 | 983292 | 0 | 0 |
T2 | 467014 | 466708 | 0 | 0 |
T4 | 14318 | 14180 | 0 | 0 |
T5 | 2574 | 2516 | 0 | 0 |
T14 | 2882 | 2412 | 0 | 0 |
T15 | 2008 | 1944 | 0 | 0 |
T16 | 5028 | 4718 | 0 | 0 |
T17 | 3620 | 3228 | 0 | 0 |
T18 | 2170 | 2022 | 0 | 0 |
T19 | 3194 | 2846 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 338181100 | 332797142 | 0 | 4824 |
T1 | 990122 | 983286 | 0 | 6 |
T2 | 467014 | 466704 | 0 | 6 |
T4 | 14318 | 14174 | 0 | 6 |
T5 | 2574 | 2510 | 0 | 6 |
T14 | 2882 | 2406 | 0 | 6 |
T15 | 2008 | 1938 | 0 | 6 |
T16 | 5028 | 4712 | 0 | 6 |
T17 | 3620 | 3222 | 0 | 6 |
T18 | 2170 | 2016 | 0 | 6 |
T19 | 3194 | 2840 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 169090550 | 166405899 | 0 | 0 |
gen_flops.OutputDelay_A | 169090550 | 166398571 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169090550 | 166405899 | 0 | 0 |
T1 | 495061 | 491646 | 0 | 0 |
T2 | 233507 | 233354 | 0 | 0 |
T4 | 7159 | 7090 | 0 | 0 |
T5 | 1287 | 1258 | 0 | 0 |
T14 | 1441 | 1206 | 0 | 0 |
T15 | 1004 | 972 | 0 | 0 |
T16 | 2514 | 2359 | 0 | 0 |
T17 | 1810 | 1614 | 0 | 0 |
T18 | 1085 | 1011 | 0 | 0 |
T19 | 1597 | 1423 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169090550 | 166398571 | 0 | 2412 |
T1 | 495061 | 491643 | 0 | 3 |
T2 | 233507 | 233352 | 0 | 3 |
T4 | 7159 | 7087 | 0 | 3 |
T5 | 1287 | 1255 | 0 | 3 |
T14 | 1441 | 1203 | 0 | 3 |
T15 | 1004 | 969 | 0 | 3 |
T16 | 2514 | 2356 | 0 | 3 |
T17 | 1810 | 1611 | 0 | 3 |
T18 | 1085 | 1008 | 0 | 3 |
T19 | 1597 | 1420 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 169090550 | 166405899 | 0 | 0 |
gen_flops.OutputDelay_A | 169090550 | 166398571 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169090550 | 166405899 | 0 | 0 |
T1 | 495061 | 491646 | 0 | 0 |
T2 | 233507 | 233354 | 0 | 0 |
T4 | 7159 | 7090 | 0 | 0 |
T5 | 1287 | 1258 | 0 | 0 |
T14 | 1441 | 1206 | 0 | 0 |
T15 | 1004 | 972 | 0 | 0 |
T16 | 2514 | 2359 | 0 | 0 |
T17 | 1810 | 1614 | 0 | 0 |
T18 | 1085 | 1011 | 0 | 0 |
T19 | 1597 | 1423 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169090550 | 166398571 | 0 | 2412 |
T1 | 495061 | 491643 | 0 | 3 |
T2 | 233507 | 233352 | 0 | 3 |
T4 | 7159 | 7087 | 0 | 3 |
T5 | 1287 | 1255 | 0 | 3 |
T14 | 1441 | 1203 | 0 | 3 |
T15 | 1004 | 969 | 0 | 3 |
T16 | 2514 | 2356 | 0 | 3 |
T17 | 1810 | 1611 | 0 | 3 |
T18 | 1085 | 1008 | 0 | 3 |
T19 | 1597 | 1420 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |