Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T37,T38,T40
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1009755318	14657	0	0
GateOpen_A	1009755318	21042	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009755318	14657	0	0
T1	2102748	251	0	0
T2	1187845	133	0	0
T3	0	31	0	0
T10	0	37	0	0
T12	0	274	0	0
T16	21834	0	0	0
T17	5713	0	0	0
T18	271152	0	0	0
T19	23625	0	0	0
T20	3778	0	0	0
T21	63361	0	0	0
T22	16342	0	0	0
T23	10689	0	0	0
T78	0	25	0	0
T110	0	4	0	0
T112	0	4	0	0
T171	0	8	0	0
T172	0	22	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009755318	21042	0	0
T1	2102748	263	0	0
T2	1187845	137	0	0
T3	0	47	0	0
T4	222294	80	0	0
T6	228888	4	0	0
T16	21834	4	0	0
T17	5713	0	0	0
T18	0	40	0	0
T20	0	4	0	0
T22	0	4	0	0
T24	3403	0	0	0
T25	9447	0	0	0
T26	31268	4	0	0
T27	13787	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	111330916	3477	0	0
GateOpen_A	111330916	5070	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330916	3477	0	0
T1	233341	61	0	0
T2	131380	32	0	0
T3	0	6	0	0
T10	0	9	0	0
T12	0	67	0	0
T16	2600	0	0	0
T17	617	0	0	0
T18	24829	0	0	0
T19	2605	0	0	0
T20	407	0	0	0
T21	7436	0	0	0
T22	1948	0	0	0
T23	1166	0	0	0
T78	0	6	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	2	0	0
T172	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330916	5070	0	0
T1	233341	64	0	0
T2	131380	33	0	0
T3	0	10	0	0
T4	14855	20	0	0
T6	23826	1	0	0
T16	2600	1	0	0
T17	617	0	0	0
T18	0	10	0	0
T20	0	1	0	0
T22	0	1	0	0
T24	358	0	0	0
T25	1047	0	0	0
T26	3851	1	0	0
T27	1616	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	222662653	3744	0	0
GateOpen_A	222662653	5337	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662653	3744	0	0
T1	466684	63	0	0
T2	262761	36	0	0
T3	0	9	0	0
T10	0	9	0	0
T12	0	71	0	0
T16	5199	0	0	0
T17	1234	0	0	0
T18	49657	0	0	0
T19	5210	0	0	0
T20	813	0	0	0
T21	14876	0	0	0
T22	3898	0	0	0
T23	2331	0	0	0
T78	0	7	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662653	5337	0	0
T1	466684	66	0	0
T2	262761	37	0	0
T3	0	13	0	0
T4	29711	20	0	0
T6	47651	1	0	0
T16	5199	1	0	0
T17	1234	0	0	0
T18	0	10	0	0
T20	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	2094	0	0	0
T26	7706	1	0	0
T27	3234	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	446837772	3725	0	0
GateOpen_A	446837772	5324	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837772	3725	0	0
T1	931870	64	0	0
T2	525480	31	0	0
T3	0	8	0	0
T10	0	9	0	0
T12	0	70	0	0
T16	9356	0	0	0
T17	2574	0	0	0
T18	131109	0	0	0
T19	10540	0	0	0
T20	1705	0	0	0
T21	27365	0	0	0
T22	6997	0	0	0
T23	4795	0	0	0
T78	0	5	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837772	5324	0	0
T1	931870	67	0	0
T2	525480	32	0	0
T3	0	12	0	0
T4	118483	20	0	0
T6	95338	1	0	0
T16	9356	1	0	0
T17	2574	0	0	0
T18	0	10	0	0
T20	0	1	0	0
T22	0	1	0	0
T24	1552	0	0	0
T25	4204	0	0	0
T26	13140	1	0	0
T27	5958	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T37,T38,T40
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	228923977	3711	0	0
GateOpen_A	228923977	5311	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228923977	3711	0	0
T1	470853	63	0	0
T2	268224	34	0	0
T3	0	8	0	0
T10	0	10	0	0
T12	0	66	0	0
T16	4679	0	0	0
T17	1288	0	0	0
T18	65557	0	0	0
T19	5270	0	0	0
T20	853	0	0	0
T21	13684	0	0	0
T22	3499	0	0	0
T23	2397	0	0	0
T78	0	7	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228923977	5311	0	0
T1	470853	66	0	0
T2	268224	35	0	0
T3	0	12	0	0
T4	59245	20	0	0
T6	62073	1	0	0
T16	4679	1	0	0
T17	1288	0	0	0
T18	0	10	0	0
T20	0	1	0	0
T22	0	1	0	0
T24	777	0	0	0
T25	2102	0	0	0
T26	6571	1	0	0
T27	2979	0	0	0