Module Definition
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Module : clkmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.63 100.00 93.15 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.63 100.00 93.15 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.63 100.00 93.15 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.46 99.15 95.79 100.00 100.00 98.81 97.01


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clkmgr_aes_trans_sva_if 100.00 100.00
clkmgr_aon_cg_aon_peri 100.00 100.00
clkmgr_aon_cg_aon_powerup 100.00 100.00
clkmgr_aon_cg_aon_secure 100.00 100.00
clkmgr_aon_cg_aon_timers 100.00 100.00
clkmgr_aon_cg_io_div2_powerup 100.00 100.00
clkmgr_aon_cg_io_div4_powerup 100.00 100.00
clkmgr_aon_cg_io_powerup 100.00 100.00
clkmgr_aon_cg_main_powerup 100.00 100.00
clkmgr_aon_cg_usb_powerup 100.00 100.00
clkmgr_cg_io_div2_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div2_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_secure 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_timers 100.00 100.00 100.00 100.00
clkmgr_cg_io_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_peri 100.00 100.00 100.00 100.00
clkmgr_cg_main_aes 100.00 100.00 100.00 100.00
clkmgr_cg_main_hmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_infra 100.00 100.00 100.00 100.00
clkmgr_cg_main_kmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_otbn 100.00 100.00 100.00 100.00
clkmgr_cg_main_secure 100.00 100.00 100.00 100.00
clkmgr_cg_usb_peri 100.00 100.00 100.00 100.00
clkmgr_csr_assert 100.00 100.00
clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
clkmgr_div4_sva_if 100.00 100.00 100.00 100.00
clkmgr_extclk_sva_if 100.00 100.00 100.00 100.00
clkmgr_hmac_trans_sva_if 100.00 100.00
clkmgr_io_div2_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_div4_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_kmac_trans_sva_if 100.00 100.00
clkmgr_lost_calib_io_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div2_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div4_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_main_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_regwen_sva_if 100.00 100.00
clkmgr_lost_calib_usb_ctrl_en_sva_if 100.00 100.00
clkmgr_otbn_trans_sva_if 100.00 100.00
clkmgr_pwrmgr_sva_if 100.00 100.00
clkmgr_sec_cm_checker_assert 100.00 100.00 100.00 100.00
clkmgr_usb_peri_sva_if 100.00 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 99.30 100.00 100.00 97.90
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_clk_aon_buf 100.00 100.00
u_clk_aon_peri_buf 100.00 100.00
u_clk_aon_powerup_buf 100.00 100.00
u_clk_aon_secure_buf 100.00 100.00
u_clk_aon_timers_buf 100.00 100.00
u_clk_io_buf 100.00 100.00
u_clk_io_div2_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div2_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div2_powerup_buf 100.00 100.00
u_clk_io_div4_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div4_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div4_powerup_buf 100.00 100.00
u_clk_io_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_powerup_buf 100.00 100.00
u_clk_main_aes_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_buf 100.00 100.00
u_clk_main_hmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_kmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_otbn_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_powerup_buf 100.00 100.00
u_clk_usb_buf 100.00 100.00
u_clk_usb_peri_cg 100.00 100.00 100.00 100.00
u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
u_clk_usb_peri_sw_en_sync 100.00 100.00 100.00
u_clk_usb_powerup_buf 100.00 100.00
u_clkmgr_byp 100.00 100.00 100.00 100.00 100.00
u_io_div2_div_scanmode_sync 100.00 100.00 100.00
u_io_div2_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div2_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_div4_div_scanmode_sync 100.00 100.00 100.00
u_io_div4_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div4_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_status 100.00 100.00 100.00
u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_main_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_main_status 100.00 100.00 100.00
u_no_scan_io_div2_div 100.00 100.00 100.00 100.00 100.00
u_no_scan_io_div4_div 100.00 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_timers 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_peri 100.00 100.00 100.00 100.00
u_reg 97.63 98.39 95.37 100.00 97.91 96.48
u_usb_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_usb_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_usb_status 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr
Line No.TotalCoveredPercent
TOTAL3434100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN48611100.00
CONT_ASSIGN51111100.00
ALWAYS55255100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN73211100.00
CONT_ASSIGN74311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN77611100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN94511100.00
CONT_ASSIGN106211100.00
CONT_ASSIGN107111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
260 1 1
266 1 1
279 1 1
309 1 1
310 1 1
408 1 1
413 1 1
414 1 1
415 1 1
418 1 1
437 1 1
462 1 1
474 1 1
486 1 1
511 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
MISSING_ELSE
699 1 1
710 1 1
721 1 1
732 1 1
743 1 1
754 1 1
765 1 1
776 1 1
819 1 1
861 1 1
903 1 1
945 1 1
1062 1 1
1071 1 1


Cond Coverage for Module : clkmgr
TotalCoveredPercent
Conditions14613693.15
Logical14613693.15
Non-Logical00
Event00

 LINE       28
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       65
 EXPRESSION (idle_i[0] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT24,T26,T27
1CoveredT5,T6,T4

 LINE       65
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       75
 EXPRESSION (idle_i[1] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT24,T26,T27
1CoveredT5,T6,T4

 LINE       75
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       85
 EXPRESSION (idle_i[2] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT24,T26,T27
1CoveredT5,T6,T4

 LINE       85
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       95
 EXPRESSION (idle_i[3] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT24,T26,T27
1CoveredT5,T6,T4

 LINE       95
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       119
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT25,T26,T27

 LINE       119
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       130
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT25,T26,T27

 LINE       130
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T4,T24

 LINE       139
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       143
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       147
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       151
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       155
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       159
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       165
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       171
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       175
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1Not Covered

 LINE       180
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       189
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       198
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       207
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       216
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       225
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       234
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       243
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       252
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT20,T34,T35
10CoveredT5,T6,T4
11CoveredT20,T34,T35

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT20,T34,T35
10CoveredT5,T6,T4
11CoveredT20,T34,T35

 LINE       261
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       266
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)
-1--2--3--4--5--6--7--8--9--10--11-StatusTests
00000000000CoveredT5,T6,T4
00000000001Not Covered
00000000010CoveredT6,T1,T2
00000000100CoveredT1,T2,T3
00000001000CoveredT5,T6,T1
00000010000CoveredT1,T2,T3
00000100000CoveredT6,T1,T2
00001000000CoveredT1,T2,T3
00010000000CoveredT12,T14,T36
00100000000CoveredT1,T2,T3
01000000000CoveredT12,T14,T36
10000000000CoveredT1,T2,T3

 LINE       270
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       279
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------
-1--2-StatusTests
00CoveredT24,T1,T2
01CoveredT5,T6,T4
10CoveredT5,T6,T4

 LINE       279
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       288
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT24,T1,T2
01CoveredT5,T6,T4
10CoveredT5,T6,T4

 LINE       288
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       297
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT24,T1,T2
01CoveredT5,T6,T4
10CoveredT5,T6,T4

 LINE       297
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       306
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT24,T1,T2
01CoveredT5,T6,T4
10CoveredT5,T6,T4

 LINE       306
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       704
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       715
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       726
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       737
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       748
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       759
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       770
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       781
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       819
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT37,T38,T39
11CoveredT5,T6,T4

 LINE       832
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       861
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT37,T38,T39
11CoveredT5,T6,T4

 LINE       874
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       903
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT37,T38,T39
11CoveredT5,T6,T4

 LINE       916
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

 LINE       945
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT37,T38,T40
11CoveredT5,T6,T4

 LINE       958
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T4
1CoveredT5,T6,T4

Toggle Coverage for Module : clkmgr
TotalCoveredPercent
Totals 106 106 100.00
Total Bits 660 660 100.00
Total Bits 0->1 330 330 100.00
Total Bits 1->0 330 330 100.00

Ports 106 106 100.00
Port Bits 660 660 100.00
Port Bits 0->1 330 330 100.00
Port Bits 1->0 330 330 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
rst_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_shadowed_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
clk_main_i Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
rst_main_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
clk_io_i Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
rst_io_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
clk_usb_i Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
rst_usb_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
clk_aon_i Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
rst_aon_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_io_div2_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_io_div4_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_main_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_io_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_io_div2_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_io_div4_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
rst_root_usb_ni Yes Yes T4,T1,T2 Yes T5,T6,T4 INPUT
tl_i.d_ready Yes Yes T6,T24,T25 Yes T5,T6,T4 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T24,T26,T27 Yes T24,T26,T27 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_address[31:0] Yes Yes T6,T4,T24 Yes T6,T4,T24 INPUT
tl_i.a_source[7:0] Yes Yes T6,T4,T24 Yes T6,T4,T24 INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_i.a_valid Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
tl_o.a_ready Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
tl_o.d_error Yes Yes T1,T2,T12 Yes T1,T2,T12 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T5,*T6,*T4 Yes T5,T6,T4 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T6,T4,T24 Yes T6,T4,T24 OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T6,*T4 Yes T5,T6,T4 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
alert_rx_i[0].ack_n Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
alert_rx_i[0].ack_p Yes Yes T5,T6,T1 Yes T5,T6,T1 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T5,T6,T4 Yes T5,T6,T4 INPUT
alert_rx_i[1].ack_p Yes Yes T20,T34,T35 Yes T20,T34,T35 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
alert_tx_o[0].alert_p Yes Yes T5,T6,T1 Yes T5,T6,T1 OUTPUT
alert_tx_o[1].alert_n Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
alert_tx_o[1].alert_p Yes Yes T20,T34,T35 Yes T20,T34,T35 OUTPUT
pwr_i.usb_ip_clk_en Yes Yes T37,T38,T40 Yes T37,T38,T40 INPUT
pwr_i.io_ip_clk_en Yes Yes T37,T38,T39 Yes T37,T38,T39 INPUT
pwr_i.main_ip_clk_en Yes Yes T37,T38,T39 Yes T37,T38,T39 INPUT
pwr_o.usb_status Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
pwr_o.io_status Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
pwr_o.main_status Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
scanmode_i[3:0] Yes Yes T24,T26,T27 Yes T5,T6,T4 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T26,T27,T1 Yes T25,T26,T27 INPUT
lc_clk_byp_req_i[3:0] Yes Yes T26,T27,T1 Yes T26,T27,T1 INPUT
lc_clk_byp_ack_o[3:0] Yes Yes T26,T27,T1 Yes T26,T27,T1 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T26,T27,T1 Yes T26,T27,T1 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T26,T27,T1 Yes T26,T27,T1 INPUT
all_clk_byp_req_o[3:0] Yes Yes T25,T26,T27 Yes T26,T27,T1 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T25,T26,T27 Yes T26,T27,T1 INPUT
hi_speed_sel_o[3:0] Yes Yes T4,T25,T26 Yes T5,T6,T4 OUTPUT
calib_rdy_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jitter_en_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
div_step_down_req_i[3:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
cg_en_o.usb_peri[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_peri[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div2_peri[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div4_peri[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div4_timers[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.main_secure[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div4_secure[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div2_infra[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_infra[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.usb_infra[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.main_infra[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.io_div4_infra[3:0] Yes Yes T4,T1,T2 Yes T5,T6,T4 OUTPUT
cg_en_o.main_otbn[3:0] Yes Yes T4,T24,T1 Yes T5,T6,T4 OUTPUT
cg_en_o.main_kmac[3:0] Yes Yes T4,T24,T1 Yes T5,T6,T4 OUTPUT
cg_en_o.main_hmac[3:0] Yes Yes T4,T24,T1 Yes T5,T6,T4 OUTPUT
cg_en_o.main_aes[3:0] Yes Yes T4,T24,T1 Yes T5,T6,T4 OUTPUT
cg_en_o.aon_timers[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_peri[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_secure[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_div2_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.usb_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.main_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_div4_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
clocks_o.clk_usb_peri Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_peri Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div2_peri Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div4_peri Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div4_timers Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_secure Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div4_secure Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div2_infra Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_infra Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_usb_infra Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_infra Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div4_infra Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_otbn Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_kmac Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_hmac Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_aes Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_aon_timers Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_aon_peri Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_aon_secure Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div2_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_usb_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_main_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_aon_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT
clocks_o.clk_io_div4_powerup Yes Yes T5,T6,T4 Yes T5,T6,T4 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : clkmgr
Line No.TotalCoveredPercent
Branches 26 26 100.00
TERNARY 704 2 2 100.00
TERNARY 715 2 2 100.00
TERNARY 726 2 2 100.00
TERNARY 737 2 2 100.00
TERNARY 748 2 2 100.00
TERNARY 759 2 2 100.00
TERNARY 770 2 2 100.00
TERNARY 781 2 2 100.00
TERNARY 832 2 2 100.00
TERNARY 874 2 2 100.00
TERNARY 916 2 2 100.00
TERNARY 958 2 2 100.00
IF 555 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 704 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 715 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 726 (clk_usb_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 737 (clk_io_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 748 (clk_io_div2_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 759 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 770 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 781 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 832 (clk_io_div4_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 874 (clk_io_div2_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 916 (clk_io_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 958 (clk_usb_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 555 if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:
-1-StatusTests
1 Covered T4,T1,T2
0 Covered T5,T6,T4


Assert Coverage for Module : clkmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 162507769 160007757 0 0
AllClkBypReqKnownO_A 162507769 160007757 0 0
CgEnKnownO_A 162507769 160007757 0 0
ClocksKownO_A 162507769 160007757 0 0
FpvSecCmClkMainAesCountCheck_A 162507769 15 0 0
FpvSecCmClkMainHmacCountCheck_A 162507769 13 0 0
FpvSecCmClkMainKmacCountCheck_A 162507769 18 0 0
FpvSecCmClkMainOtbnCountCheck_A 162507769 22 0 0
FpvSecCmRegWeOnehotCheck_A 162507769 60 0 0
IoClkBypReqKnownO_A 162507769 160007757 0 0
JitterEnableKnownO_A 162507769 160007757 0 0
LcCtrlClkBypAckKnownO_A 162507769 160007757 0 0
PwrMgrKnownO_A 162507769 160007757 0 0
TlAReadyKnownO_A 162507769 160007757 0 0
TlDValidKnownO_A 162507769 160007757 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

AllClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

CgEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

ClocksKownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

FpvSecCmClkMainAesCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 15 0 0
T36 496332 0 0 0
T41 10794 1 0 0
T42 0 4 0 0
T43 0 10 0 0
T44 1850 0 0 0
T45 1656 0 0 0
T46 1569 0 0 0
T47 2685 0 0 0
T48 1750 0 0 0
T49 1741 0 0 0
T50 1480 0 0 0
T51 1762 0 0 0

FpvSecCmClkMainHmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 13 0 0
T42 13931 4 0 0
T43 0 9 0 0
T52 1343 0 0 0
T53 3481 0 0 0
T54 1310 0 0 0
T55 2773 0 0 0
T56 1042 0 0 0
T57 1138 0 0 0
T58 1238 0 0 0
T59 1830 0 0 0
T60 30690 0 0 0

FpvSecCmClkMainKmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 18 0 0
T42 13931 4 0 0
T43 0 14 0 0
T52 1343 0 0 0
T53 3481 0 0 0
T54 1310 0 0 0
T55 2773 0 0 0
T56 1042 0 0 0
T57 1138 0 0 0
T58 1238 0 0 0
T59 1830 0 0 0
T60 30690 0 0 0

FpvSecCmClkMainOtbnCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 22 0 0
T36 496332 0 0 0
T41 10794 2 0 0
T42 0 6 0 0
T43 0 14 0 0
T44 1850 0 0 0
T45 1656 0 0 0
T46 1569 0 0 0
T47 2685 0 0 0
T48 1750 0 0 0
T49 1741 0 0 0
T50 1480 0 0 0
T51 1762 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 60 0 0
T36 496332 0 0 0
T41 10794 10 0 0
T42 0 10 0 0
T43 0 20 0 0
T44 1850 0 0 0
T45 1656 0 0 0
T46 1569 0 0 0
T47 2685 0 0 0
T48 1750 0 0 0
T49 1741 0 0 0
T50 1480 0 0 0
T51 1762 0 0 0
T61 0 10 0 0
T62 0 10 0 0

IoClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

JitterEnableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

LcCtrlClkBypAckKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

PwrMgrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 160007757 0 0
T1 236861 236701 0 0
T2 141198 141171 0 0
T4 118482 5595 0 0
T5 93426 93324 0 0
T6 33828 33807 0 0
T16 1363 1334 0 0
T24 1569 1363 0 0
T25 700 673 0 0
T26 1368 1350 0 0
T27 1613 1580 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%