Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	812538845	76459	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812538845	76459	0	0
T1	1184305	979	0	0
T2	705990	591	0	0
T3	0	99	0	0
T9	0	50	0	0
T10	0	114	0	0
T11	0	39	0	0
T12	0	3330	0	0
T13	0	108	0	0
T14	0	216	0	0
T15	0	319	0	0
T16	6815	0	0	0
T17	6440	0	0	0
T18	54625	0	0	0
T19	12625	0	0	0
T20	8615	0	0	0
T21	7120	0	0	0
T22	4740	0	0	0
T23	12485	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162507769	11136	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	11136	0	0
T1	236861	157	0	0
T2	141198	94	0	0
T3	0	16	0	0
T9	0	8	0	0
T10	0	17	0	0
T11	0	6	0	0
T12	0	423	0	0
T13	0	19	0	0
T14	0	28	0	0
T15	0	42	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162507769	15353	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	15353	0	0
T1	236861	198	0	0
T2	141198	117	0	0
T3	0	20	0	0
T9	0	10	0	0
T10	0	22	0	0
T11	0	8	0	0
T12	0	660	0	0
T13	0	23	0	0
T14	0	43	0	0
T15	0	64	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162507769	23542	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	23542	0	0
T1	236861	273	0	0
T2	141198	170	0	0
T3	0	27	0	0
T9	0	14	0	0
T10	0	39	0	0
T11	0	11	0	0
T12	0	1106	0	0
T13	0	26	0	0
T14	0	72	0	0
T15	0	108	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162507769	10973	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	10973	0	0
T1	236861	153	0	0
T2	141198	91	0	0
T3	0	16	0	0
T9	0	8	0	0
T10	0	14	0	0
T11	0	6	0	0
T12	0	476	0	0
T13	0	19	0	0
T14	0	28	0	0
T15	0	40	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162507769	15455	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	15455	0	0
T1	236861	198	0	0
T2	141198	119	0	0
T3	0	20	0	0
T9	0	10	0	0
T10	0	22	0	0
T11	0	8	0	0
T12	0	665	0	0
T13	0	21	0	0
T14	0	45	0	0
T15	0	65	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0