Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
15179031 |
15170373 |
0 |
0 |
T2 |
8713824 |
8712353 |
0 |
0 |
T4 |
3110337 |
325962 |
0 |
0 |
T5 |
3292423 |
3288823 |
0 |
0 |
T6 |
1907650 |
1906516 |
0 |
0 |
T16 |
137983 |
135510 |
0 |
0 |
T24 |
41473 |
36382 |
0 |
0 |
T25 |
62861 |
60871 |
0 |
0 |
T26 |
186739 |
184504 |
0 |
0 |
T27 |
98180 |
96526 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
975046614 |
960004740 |
0 |
14490 |
T1 |
1421166 |
1420194 |
0 |
18 |
T2 |
847188 |
847014 |
0 |
18 |
T4 |
710892 |
33192 |
0 |
18 |
T5 |
560556 |
559926 |
0 |
18 |
T6 |
202968 |
202824 |
0 |
18 |
T16 |
8178 |
7986 |
0 |
18 |
T24 |
9414 |
8160 |
0 |
18 |
T25 |
4200 |
4020 |
0 |
18 |
T26 |
8208 |
8082 |
0 |
18 |
T27 |
9678 |
9462 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
5329307 |
5325665 |
0 |
21 |
T2 |
3040644 |
3040040 |
0 |
21 |
T4 |
849142 |
39592 |
0 |
21 |
T5 |
998626 |
997350 |
0 |
21 |
T6 |
656254 |
655780 |
0 |
21 |
T16 |
51066 |
49936 |
0 |
21 |
T24 |
11158 |
9674 |
0 |
21 |
T25 |
23120 |
22207 |
0 |
21 |
T26 |
70623 |
69658 |
0 |
21 |
T27 |
34008 |
33296 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
202130 |
0 |
0 |
T1 |
5329307 |
2706 |
0 |
0 |
T2 |
3040644 |
1117 |
0 |
0 |
T3 |
0 |
209 |
0 |
0 |
T4 |
493696 |
84 |
0 |
0 |
T5 |
682532 |
4 |
0 |
0 |
T6 |
493260 |
4 |
0 |
0 |
T16 |
51066 |
84 |
0 |
0 |
T17 |
5150 |
11 |
0 |
0 |
T18 |
152959 |
0 |
0 |
0 |
T19 |
15590 |
0 |
0 |
0 |
T20 |
5151 |
0 |
0 |
0 |
T21 |
1424 |
86 |
0 |
0 |
T22 |
0 |
43 |
0 |
0 |
T24 |
6468 |
43 |
0 |
0 |
T25 |
22420 |
10 |
0 |
0 |
T26 |
70623 |
185 |
0 |
0 |
T27 |
34008 |
166 |
0 |
0 |
T108 |
0 |
30 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8428558 |
8424488 |
0 |
0 |
T2 |
4825992 |
4825273 |
0 |
0 |
T4 |
1550303 |
252359 |
0 |
0 |
T5 |
1733241 |
1731508 |
0 |
0 |
T6 |
1048428 |
1047873 |
0 |
0 |
T16 |
78739 |
77549 |
0 |
0 |
T24 |
20901 |
18509 |
0 |
0 |
T25 |
35541 |
34605 |
0 |
0 |
T26 |
107908 |
106725 |
0 |
0 |
T27 |
54494 |
53729 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446837348 |
442677865 |
0 |
0 |
T1 |
931869 |
931229 |
0 |
0 |
T2 |
525480 |
525376 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
129242 |
129039 |
0 |
0 |
T6 |
95338 |
95259 |
0 |
0 |
T16 |
9356 |
9153 |
0 |
0 |
T24 |
1552 |
1349 |
0 |
0 |
T25 |
4204 |
4042 |
0 |
0 |
T26 |
13139 |
12963 |
0 |
0 |
T27 |
5958 |
5837 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446837348 |
442671034 |
0 |
2415 |
T1 |
931869 |
931227 |
0 |
3 |
T2 |
525480 |
525374 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
129242 |
129036 |
0 |
3 |
T6 |
95338 |
95256 |
0 |
3 |
T16 |
9356 |
9150 |
0 |
3 |
T24 |
1552 |
1346 |
0 |
3 |
T25 |
4204 |
4039 |
0 |
3 |
T26 |
13139 |
12960 |
0 |
3 |
T27 |
5958 |
5834 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446837348 |
29273 |
0 |
0 |
T1 |
931869 |
378 |
0 |
0 |
T2 |
525480 |
48 |
0 |
0 |
T3 |
0 |
91 |
0 |
0 |
T16 |
9356 |
30 |
0 |
0 |
T17 |
2574 |
5 |
0 |
0 |
T18 |
131109 |
0 |
0 |
0 |
T19 |
10540 |
0 |
0 |
0 |
T20 |
1705 |
0 |
0 |
0 |
T21 |
0 |
49 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T25 |
4204 |
3 |
0 |
0 |
T26 |
13139 |
37 |
0 |
0 |
T27 |
5958 |
62 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T26,T27,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T26,T27,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T26,T27,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T26,T27,T1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T1 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T1 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T1 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T27,T1 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
18563 |
0 |
0 |
T1 |
236861 |
256 |
0 |
0 |
T2 |
141198 |
26 |
0 |
0 |
T3 |
0 |
56 |
0 |
0 |
T16 |
1363 |
11 |
0 |
0 |
T17 |
1288 |
4 |
0 |
0 |
T18 |
10925 |
0 |
0 |
0 |
T19 |
2525 |
0 |
0 |
0 |
T20 |
1723 |
0 |
0 |
0 |
T21 |
1424 |
13 |
0 |
0 |
T22 |
0 |
5 |
0 |
0 |
T26 |
1368 |
39 |
0 |
0 |
T27 |
1613 |
29 |
0 |
0 |
T108 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T25,T26,T27 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T25,T26,T27 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
20871 |
0 |
0 |
T1 |
236861 |
308 |
0 |
0 |
T2 |
141198 |
42 |
0 |
0 |
T3 |
0 |
62 |
0 |
0 |
T16 |
1363 |
19 |
0 |
0 |
T17 |
1288 |
2 |
0 |
0 |
T18 |
10925 |
0 |
0 |
0 |
T19 |
2525 |
0 |
0 |
0 |
T20 |
1723 |
0 |
0 |
0 |
T21 |
0 |
24 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T25 |
700 |
3 |
0 |
0 |
T26 |
1368 |
53 |
0 |
0 |
T27 |
1613 |
22 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
474372108 |
0 |
0 |
T1 |
980929 |
980748 |
0 |
0 |
T2 |
558192 |
558141 |
0 |
0 |
T4 |
123424 |
61869 |
0 |
0 |
T5 |
170633 |
170521 |
0 |
0 |
T6 |
123315 |
123275 |
0 |
0 |
T16 |
9746 |
9677 |
0 |
0 |
T24 |
1617 |
1491 |
0 |
0 |
T25 |
4379 |
4339 |
0 |
0 |
T26 |
13687 |
13547 |
0 |
0 |
T27 |
6206 |
6180 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
474372108 |
0 |
0 |
T1 |
980929 |
980748 |
0 |
0 |
T2 |
558192 |
558141 |
0 |
0 |
T4 |
123424 |
61869 |
0 |
0 |
T5 |
170633 |
170521 |
0 |
0 |
T6 |
123315 |
123275 |
0 |
0 |
T16 |
9746 |
9677 |
0 |
0 |
T24 |
1617 |
1491 |
0 |
0 |
T25 |
4379 |
4339 |
0 |
0 |
T26 |
13687 |
13547 |
0 |
0 |
T27 |
6206 |
6180 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446837348 |
444791028 |
0 |
0 |
T1 |
931869 |
931695 |
0 |
0 |
T2 |
525480 |
525430 |
0 |
0 |
T4 |
118482 |
59410 |
0 |
0 |
T5 |
129242 |
129135 |
0 |
0 |
T6 |
95338 |
95300 |
0 |
0 |
T16 |
9356 |
9290 |
0 |
0 |
T24 |
1552 |
1431 |
0 |
0 |
T25 |
4204 |
4165 |
0 |
0 |
T26 |
13139 |
13004 |
0 |
0 |
T27 |
5958 |
5933 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446837348 |
444791028 |
0 |
0 |
T1 |
931869 |
931695 |
0 |
0 |
T2 |
525480 |
525430 |
0 |
0 |
T4 |
118482 |
59410 |
0 |
0 |
T5 |
129242 |
129135 |
0 |
0 |
T6 |
95338 |
95300 |
0 |
0 |
T16 |
9356 |
9290 |
0 |
0 |
T24 |
1552 |
1431 |
0 |
0 |
T25 |
4204 |
4165 |
0 |
0 |
T26 |
13139 |
13004 |
0 |
0 |
T27 |
5958 |
5933 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222662241 |
222662241 |
0 |
0 |
T1 |
466684 |
466684 |
0 |
0 |
T2 |
262760 |
262760 |
0 |
0 |
T4 |
29710 |
29710 |
0 |
0 |
T5 |
64568 |
64568 |
0 |
0 |
T6 |
47650 |
47650 |
0 |
0 |
T16 |
5198 |
5198 |
0 |
0 |
T24 |
716 |
716 |
0 |
0 |
T25 |
2094 |
2094 |
0 |
0 |
T26 |
7705 |
7705 |
0 |
0 |
T27 |
3234 |
3234 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222662241 |
222662241 |
0 |
0 |
T1 |
466684 |
466684 |
0 |
0 |
T2 |
262760 |
262760 |
0 |
0 |
T4 |
29710 |
29710 |
0 |
0 |
T5 |
64568 |
64568 |
0 |
0 |
T6 |
47650 |
47650 |
0 |
0 |
T16 |
5198 |
5198 |
0 |
0 |
T24 |
716 |
716 |
0 |
0 |
T25 |
2094 |
2094 |
0 |
0 |
T26 |
7705 |
7705 |
0 |
0 |
T27 |
3234 |
3234 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111330503 |
111330503 |
0 |
0 |
T1 |
233341 |
233341 |
0 |
0 |
T2 |
131380 |
131380 |
0 |
0 |
T4 |
14855 |
14855 |
0 |
0 |
T5 |
32284 |
32284 |
0 |
0 |
T6 |
23825 |
23825 |
0 |
0 |
T16 |
2599 |
2599 |
0 |
0 |
T24 |
358 |
358 |
0 |
0 |
T25 |
1047 |
1047 |
0 |
0 |
T26 |
3851 |
3851 |
0 |
0 |
T27 |
1616 |
1616 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111330503 |
111330503 |
0 |
0 |
T1 |
233341 |
233341 |
0 |
0 |
T2 |
131380 |
131380 |
0 |
0 |
T4 |
14855 |
14855 |
0 |
0 |
T5 |
32284 |
32284 |
0 |
0 |
T6 |
23825 |
23825 |
0 |
0 |
T16 |
2599 |
2599 |
0 |
0 |
T24 |
358 |
358 |
0 |
0 |
T25 |
1047 |
1047 |
0 |
0 |
T26 |
3851 |
3851 |
0 |
0 |
T27 |
1616 |
1616 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228923556 |
227883803 |
0 |
0 |
T1 |
470853 |
470766 |
0 |
0 |
T2 |
268224 |
268200 |
0 |
0 |
T4 |
59244 |
29697 |
0 |
0 |
T5 |
93426 |
93372 |
0 |
0 |
T6 |
62072 |
62053 |
0 |
0 |
T16 |
4678 |
4645 |
0 |
0 |
T24 |
776 |
715 |
0 |
0 |
T25 |
2101 |
2082 |
0 |
0 |
T26 |
6570 |
6502 |
0 |
0 |
T27 |
2978 |
2966 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228923556 |
227883803 |
0 |
0 |
T1 |
470853 |
470766 |
0 |
0 |
T2 |
268224 |
268200 |
0 |
0 |
T4 |
59244 |
29697 |
0 |
0 |
T5 |
93426 |
93372 |
0 |
0 |
T6 |
62072 |
62053 |
0 |
0 |
T16 |
4678 |
4645 |
0 |
0 |
T24 |
776 |
715 |
0 |
0 |
T25 |
2101 |
2082 |
0 |
0 |
T26 |
6570 |
6502 |
0 |
0 |
T27 |
2978 |
2966 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160000790 |
0 |
2415 |
T1 |
236861 |
236699 |
0 |
3 |
T2 |
141198 |
141169 |
0 |
3 |
T4 |
118482 |
5532 |
0 |
3 |
T5 |
93426 |
93321 |
0 |
3 |
T6 |
33828 |
33804 |
0 |
3 |
T16 |
1363 |
1331 |
0 |
3 |
T24 |
1569 |
1360 |
0 |
3 |
T25 |
700 |
670 |
0 |
3 |
T26 |
1368 |
1347 |
0 |
3 |
T27 |
1613 |
1577 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
160007757 |
0 |
0 |
T1 |
236861 |
236701 |
0 |
0 |
T2 |
141198 |
141171 |
0 |
0 |
T4 |
118482 |
5595 |
0 |
0 |
T5 |
93426 |
93324 |
0 |
0 |
T6 |
33828 |
33807 |
0 |
0 |
T16 |
1363 |
1334 |
0 |
0 |
T24 |
1569 |
1363 |
0 |
0 |
T25 |
700 |
673 |
0 |
0 |
T26 |
1368 |
1350 |
0 |
0 |
T27 |
1613 |
1580 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472108173 |
0 |
2415 |
T1 |
980929 |
980260 |
0 |
3 |
T2 |
558192 |
558082 |
0 |
3 |
T4 |
123424 |
5749 |
0 |
3 |
T5 |
170633 |
170418 |
0 |
3 |
T6 |
123315 |
123229 |
0 |
3 |
T16 |
9746 |
9531 |
0 |
3 |
T24 |
1617 |
1402 |
0 |
3 |
T25 |
4379 |
4207 |
0 |
3 |
T26 |
13687 |
13501 |
0 |
3 |
T27 |
6206 |
6077 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
33095 |
0 |
0 |
T1 |
980929 |
425 |
0 |
0 |
T2 |
558192 |
265 |
0 |
0 |
T4 |
123424 |
21 |
0 |
0 |
T5 |
170633 |
1 |
0 |
0 |
T6 |
123315 |
1 |
0 |
0 |
T16 |
9746 |
9 |
0 |
0 |
T24 |
1617 |
11 |
0 |
0 |
T25 |
4379 |
1 |
0 |
0 |
T26 |
13687 |
17 |
0 |
0 |
T27 |
6206 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472108173 |
0 |
2415 |
T1 |
980929 |
980260 |
0 |
3 |
T2 |
558192 |
558082 |
0 |
3 |
T4 |
123424 |
5749 |
0 |
3 |
T5 |
170633 |
170418 |
0 |
3 |
T6 |
123315 |
123229 |
0 |
3 |
T16 |
9746 |
9531 |
0 |
3 |
T24 |
1617 |
1402 |
0 |
3 |
T25 |
4379 |
4207 |
0 |
3 |
T26 |
13687 |
13501 |
0 |
3 |
T27 |
6206 |
6077 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
33329 |
0 |
0 |
T1 |
980929 |
438 |
0 |
0 |
T2 |
558192 |
251 |
0 |
0 |
T4 |
123424 |
21 |
0 |
0 |
T5 |
170633 |
1 |
0 |
0 |
T6 |
123315 |
1 |
0 |
0 |
T16 |
9746 |
5 |
0 |
0 |
T24 |
1617 |
11 |
0 |
0 |
T25 |
4379 |
1 |
0 |
0 |
T26 |
13687 |
11 |
0 |
0 |
T27 |
6206 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472108173 |
0 |
2415 |
T1 |
980929 |
980260 |
0 |
3 |
T2 |
558192 |
558082 |
0 |
3 |
T4 |
123424 |
5749 |
0 |
3 |
T5 |
170633 |
170418 |
0 |
3 |
T6 |
123315 |
123229 |
0 |
3 |
T16 |
9746 |
9531 |
0 |
3 |
T24 |
1617 |
1402 |
0 |
3 |
T25 |
4379 |
4207 |
0 |
3 |
T26 |
13687 |
13501 |
0 |
3 |
T27 |
6206 |
6077 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
33610 |
0 |
0 |
T1 |
980929 |
475 |
0 |
0 |
T2 |
558192 |
236 |
0 |
0 |
T4 |
123424 |
21 |
0 |
0 |
T5 |
170633 |
1 |
0 |
0 |
T6 |
123315 |
1 |
0 |
0 |
T16 |
9746 |
1 |
0 |
0 |
T24 |
1617 |
11 |
0 |
0 |
T25 |
4379 |
1 |
0 |
0 |
T26 |
13687 |
19 |
0 |
0 |
T27 |
6206 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472108173 |
0 |
2415 |
T1 |
980929 |
980260 |
0 |
3 |
T2 |
558192 |
558082 |
0 |
3 |
T4 |
123424 |
5749 |
0 |
3 |
T5 |
170633 |
170418 |
0 |
3 |
T6 |
123315 |
123229 |
0 |
3 |
T16 |
9746 |
9531 |
0 |
3 |
T24 |
1617 |
1402 |
0 |
3 |
T25 |
4379 |
4207 |
0 |
3 |
T26 |
13687 |
13501 |
0 |
3 |
T27 |
6206 |
6077 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
33389 |
0 |
0 |
T1 |
980929 |
426 |
0 |
0 |
T2 |
558192 |
249 |
0 |
0 |
T4 |
123424 |
21 |
0 |
0 |
T5 |
170633 |
1 |
0 |
0 |
T6 |
123315 |
1 |
0 |
0 |
T16 |
9746 |
9 |
0 |
0 |
T24 |
1617 |
10 |
0 |
0 |
T25 |
4379 |
1 |
0 |
0 |
T26 |
13687 |
9 |
0 |
0 |
T27 |
6206 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476560808 |
472115066 |
0 |
0 |
T1 |
980929 |
980262 |
0 |
0 |
T2 |
558192 |
558084 |
0 |
0 |
T4 |
123424 |
5812 |
0 |
0 |
T5 |
170633 |
170421 |
0 |
0 |
T6 |
123315 |
123232 |
0 |
0 |
T16 |
9746 |
9534 |
0 |
0 |
T24 |
1617 |
1405 |
0 |
0 |
T25 |
4379 |
4210 |
0 |
0 |
T26 |
13687 |
13504 |
0 |
0 |
T27 |
6206 |
6080 |
0 |
0 |