Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	162507769	159862961	0	0
AllClkBypReqTrue_A	162507769	142519	0	0
IoClkBypReqFalse_A	162507769	159775669	0	2415
IoClkBypReqTrue_A	162507769	225257	0	0
LcClkBypAckFalse_A	162507769	159874593	0	0
LcClkBypAckTrue_A	162507769	130887	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	159862961	0	0
T1	236861	236329	0	0
T2	141198	141151	0	0
T4	118482	5574	0	0
T5	93426	93323	0	0
T6	33828	33806	0	0
T16	1363	1208	0	0
T24	1569	1362	0	0
T25	700	659	0	0
T26	1368	1155	0	0
T27	1613	1527	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	142519	0	0
T1	236861	3711	0	0
T2	141198	191	0	0
T3	0	300	0	0
T16	1363	125	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	0	140	0	0
T22	0	89	0	0
T25	700	13	0	0
T26	1368	194	0	0
T27	1613	52	0	0
T108	0	90	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	159775669	0	2415
T1	236861	236197	0	3
T2	141198	141136	0	3
T4	118482	5532	0	3
T5	93426	93321	0	3
T6	33828	33804	0	3
T16	1363	1173	0	3
T24	1569	1360	0	3
T25	700	670	0	3
T26	1368	1085	0	3
T27	1613	1335	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	225257	0	0
T1	236861	5013	0	0
T2	141198	331	0	0
T3	0	635	0	0
T16	1363	158	0	0
T17	1288	40	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	161	0	0
T22	0	50	0	0
T26	1368	262	0	0
T27	1613	242	0	0
T108	0	235	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	159874593	0	0
T1	236861	236363	0	0
T2	141198	141151	0	0
T4	118482	5574	0	0
T5	93426	93323	0	0
T6	33828	33806	0	0
T16	1363	1226	0	0
T24	1569	1362	0	0
T25	700	672	0	0
T26	1368	1252	0	0
T27	1613	1451	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162507769	130887	0	0
T1	236861	3367	0	0
T2	141198	192	0	0
T3	0	346	0	0
T16	1363	107	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	111	0	0
T22	0	42	0	0
T26	1368	97	0	0
T27	1613	128	0	0
T108	0	145	0	0
T109	0	37	0	0