Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1906245032	15247	0	0
TransStop_A	1906245032	7692	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906245032	15247	0	0
T1	3923716	224	0	0
T2	2232768	185	0	0
T3	0	109	0	0
T16	38984	0	0	0
T17	10728	0	0	0
T18	546304	0	0	0
T19	43920	39	0	0
T23	0	21	0	0
T24	6472	6	0	0
T25	17516	0	0	0
T26	54752	0	0	0
T27	24824	0	0	0
T78	0	65	0	0
T110	0	4	0	0
T111	0	25	0	0
T112	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906245032	7692	0	0
T1	3923716	108	0	0
T2	2232768	93	0	0
T3	0	52	0	0
T10	0	3	0	0
T16	38984	0	0	0
T17	10728	0	0	0
T18	546304	0	0	0
T19	43920	16	0	0
T23	0	5	0	0
T24	6472	4	0	0
T25	17516	0	0	0
T26	54752	0	0	0
T27	24824	0	0	0
T78	0	32	0	0
T110	0	4	0	0
T111	0	13	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476561258	3791	0	0
TransStop_A	476561258	1921	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	3791	0	0
T1	980929	56	0	0
T2	558192	43	0	0
T3	0	34	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	7	0	0
T23	0	5	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	1921	0	0
T1	980929	27	0	0
T2	558192	21	0	0
T3	0	17	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	3	0	0
T23	0	1	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	9	0	0
T110	0	1	0	0
T111	0	4	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476561258	3807	0	0
TransStop_A	476561258	1907	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	3807	0	0
T1	980929	55	0	0
T2	558192	48	0	0
T3	0	19	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	10	0	0
T23	0	6	0	0
T24	1618	2	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	15	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	1907	0	0
T1	980929	28	0	0
T2	558192	23	0	0
T3	0	10	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	3	0	0
T23	0	1	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	6	0	0
T110	0	1	0	0
T111	0	2	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476561258	3794	0	0
TransStop_A	476561258	1924	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	3794	0	0
T1	980929	56	0	0
T2	558192	48	0	0
T3	0	29	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	2	0	0
T24	1618	2	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	1924	0	0
T1	980929	27	0	0
T2	558192	25	0	0
T3	0	13	0	0
T10	0	3	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	6	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	8	0	0
T110	0	1	0	0
T111	0	4	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476561258	3855	0	0
TransStop_A	476561258	1940	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	3855	0	0
T1	980929	57	0	0
T2	558192	46	0	0
T3	0	27	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	8	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	5	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476561258	1940	0	0
T1	980929	26	0	0
T2	558192	24	0	0
T3	0	12	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	4	0	0
T23	0	3	0	0
T24	1618	1	0	0
T25	4379	0	0	0
T26	13688	0	0	0
T27	6206	0	0	0
T78	0	9	0	0
T110	0	1	0	0
T111	0	3	0	0
T112	0	1	0	0