Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163349174	5405147	0	0
clk_enables_rd_A	163349174	42170	0	0
clk_hints_rd_A	163349174	36403	0	0
extclk_ctrl_rd_A	163349174	47284	0	0
extclk_ctrl_regwen_rd_A	163349174	35592	0	0
jitter_enable_rd_A	163349174	53122	0	0
jitter_regwen_rd_A	163349174	39059	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	5405147	0	0
T1	236861	66154	0	0
T2	141198	48245	0	0
T12	0	127197	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T30	0	48590	0	0
T72	0	140101	0	0
T73	0	95490	0	0
T74	0	58122	0	0
T75	0	108261	0	0
T76	0	86057	0	0
T77	0	135863	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	42170	0	0
T1	236861	2489	0	0
T2	141198	0	0	0
T10	0	5	0	0
T12	0	5040	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T135	0	2	0	0
T136	0	18	0	0
T137	0	11	0	0
T138	0	10	0	0
T139	0	1	0	0
T140	0	4	0	0
T141	0	1886	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	36403	0	0
T1	236861	2111	0	0
T2	141198	0	0	0
T10	0	5	0	0
T12	0	4699	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T136	0	12	0	0
T137	0	4	0	0
T138	0	11	0	0
T140	0	3	0	0
T141	0	1477	0	0
T142	0	3344	0	0
T143	0	5156	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	47284	0	0
T1	236861	3001	0	0
T2	141198	0	0	0
T10	0	63	0	0
T12	0	5489	0	0
T16	1363	26	0	0
T17	1288	0	0	0
T18	10925	60	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	26	0	0
T22	948	0	0	0
T23	2497	0	0	0
T89	0	46	0	0
T144	0	43	0	0
T145	0	43	0	0
T146	0	44	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	35592	0	0
T1	236861	2165	0	0
T2	141198	0	0	0
T12	0	4439	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	32	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T107	0	61	0	0
T141	0	1547	0	0
T142	0	3516	0	0
T143	0	5213	0	0
T147	0	45	0	0
T148	0	6	0	0
T149	0	22	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	53122	0	0
T1	236861	3422	0	0
T2	141198	0	0	0
T10	0	248	0	0
T12	0	5540	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T135	0	107	0	0
T136	0	440	0	0
T137	0	240	0	0
T138	0	264	0	0
T139	0	114	0	0
T140	0	105	0	0
T141	0	2183	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	39059	0	0
T1	236861	2485	0	0
T2	141198	0	0	0
T12	0	4926	0	0
T16	1363	0	0	0
T17	1288	0	0	0
T18	10925	0	0	0
T19	2525	0	0	0
T20	1723	0	0	0
T21	1424	0	0	0
T22	948	0	0	0
T23	2497	0	0	0
T141	0	1827	0	0
T142	0	4154	0	0
T143	0	5681	0	0
T150	0	2647	0	0
T151	0	1841	0	0
T152	0	4631	0	0
T153	0	1961	0	0
T154	0	2752	0	0