SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T4,T24 |
1 | 0 | Covered | T26,T27,T1 |
1 | 1 | Covered | T25,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 446837772 | 4629 | 0 | 0 |
g_div2.Div2Whole_A | 446837772 | 5608 | 0 | 0 |
g_div4.Div4Stepped_A | 222662653 | 4525 | 0 | 0 |
g_div4.Div4Whole_A | 222662653 | 5263 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 446837772 | 4629 | 0 | 0 |
T1 | 931870 | 81 | 0 | 0 |
T2 | 525480 | 7 | 0 | 0 |
T3 | 0 | 13 | 0 | 0 |
T16 | 9356 | 6 | 0 | 0 |
T17 | 2574 | 0 | 0 | 0 |
T18 | 131109 | 0 | 0 | 0 |
T19 | 10540 | 0 | 0 | 0 |
T20 | 1705 | 0 | 0 | 0 |
T21 | 0 | 6 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 4204 | 1 | 0 | 0 |
T26 | 13140 | 8 | 0 | 0 |
T27 | 5958 | 7 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 446837772 | 5608 | 0 | 0 |
T1 | 931870 | 82 | 0 | 0 |
T2 | 525480 | 8 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T16 | 9356 | 6 | 0 | 0 |
T17 | 2574 | 0 | 0 | 0 |
T18 | 131109 | 0 | 0 | 0 |
T19 | 10540 | 0 | 0 | 0 |
T20 | 1705 | 0 | 0 | 0 |
T21 | 0 | 7 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 4204 | 1 | 0 | 0 |
T26 | 13140 | 8 | 0 | 0 |
T27 | 5958 | 9 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222662653 | 4525 | 0 | 0 |
T1 | 466684 | 81 | 0 | 0 |
T2 | 262761 | 7 | 0 | 0 |
T3 | 0 | 13 | 0 | 0 |
T16 | 5199 | 6 | 0 | 0 |
T17 | 1234 | 0 | 0 | 0 |
T18 | 49657 | 0 | 0 | 0 |
T19 | 5210 | 0 | 0 | 0 |
T20 | 813 | 0 | 0 | 0 |
T21 | 0 | 6 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 2094 | 1 | 0 | 0 |
T26 | 7706 | 8 | 0 | 0 |
T27 | 3234 | 7 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222662653 | 5263 | 0 | 0 |
T1 | 466684 | 82 | 0 | 0 |
T2 | 262761 | 8 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T16 | 5199 | 6 | 0 | 0 |
T17 | 1234 | 0 | 0 | 0 |
T18 | 49657 | 0 | 0 | 0 |
T19 | 5210 | 0 | 0 | 0 |
T20 | 813 | 0 | 0 | 0 |
T21 | 0 | 7 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T25 | 2094 | 1 | 0 | 0 |
T26 | 7706 | 8 | 0 | 0 |
T27 | 3234 | 9 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T4,T24 |
1 | 0 | Covered | T26,T27,T1 |
1 | 1 | Covered | T25,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 446837772 | 4629 | 0 | 0 |
g_div2.Div2Whole_A | 446837772 | 5608 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 446837772 | 4629 | 0 | 0 |
T1 | 931870 | 81 | 0 | 0 |
T2 | 525480 | 7 | 0 | 0 |
T3 | 0 | 13 | 0 | 0 |
T16 | 9356 | 6 | 0 | 0 |
T17 | 2574 | 0 | 0 | 0 |
T18 | 131109 | 0 | 0 | 0 |
T19 | 10540 | 0 | 0 | 0 |
T20 | 1705 | 0 | 0 | 0 |
T21 | 0 | 6 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 4204 | 1 | 0 | 0 |
T26 | 13140 | 8 | 0 | 0 |
T27 | 5958 | 7 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 446837772 | 5608 | 0 | 0 |
T1 | 931870 | 82 | 0 | 0 |
T2 | 525480 | 8 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T16 | 9356 | 6 | 0 | 0 |
T17 | 2574 | 0 | 0 | 0 |
T18 | 131109 | 0 | 0 | 0 |
T19 | 10540 | 0 | 0 | 0 |
T20 | 1705 | 0 | 0 | 0 |
T21 | 0 | 7 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 4204 | 1 | 0 | 0 |
T26 | 13140 | 8 | 0 | 0 |
T27 | 5958 | 9 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T4,T24 |
1 | 0 | Covered | T26,T27,T1 |
1 | 1 | Covered | T25,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 222662653 | 4525 | 0 | 0 |
g_div4.Div4Whole_A | 222662653 | 5263 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222662653 | 4525 | 0 | 0 |
T1 | 466684 | 81 | 0 | 0 |
T2 | 262761 | 7 | 0 | 0 |
T3 | 0 | 13 | 0 | 0 |
T16 | 5199 | 6 | 0 | 0 |
T17 | 1234 | 0 | 0 | 0 |
T18 | 49657 | 0 | 0 | 0 |
T19 | 5210 | 0 | 0 | 0 |
T20 | 813 | 0 | 0 | 0 |
T21 | 0 | 6 | 0 | 0 |
T22 | 0 | 5 | 0 | 0 |
T25 | 2094 | 1 | 0 | 0 |
T26 | 7706 | 8 | 0 | 0 |
T27 | 3234 | 7 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222662653 | 5263 | 0 | 0 |
T1 | 466684 | 82 | 0 | 0 |
T2 | 262761 | 8 | 0 | 0 |
T3 | 0 | 17 | 0 | 0 |
T16 | 5199 | 6 | 0 | 0 |
T17 | 1234 | 0 | 0 | 0 |
T18 | 49657 | 0 | 0 | 0 |
T19 | 5210 | 0 | 0 | 0 |
T20 | 813 | 0 | 0 | 0 |
T21 | 0 | 7 | 0 | 0 |
T22 | 0 | 4 | 0 | 0 |
T25 | 2094 | 1 | 0 | 0 |
T26 | 7706 | 8 | 0 | 0 |
T27 | 3234 | 9 | 0 | 0 |
T108 | 0 | 11 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |