Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T4,T24
10CoveredT26,T27,T1
11CoveredT25,T26,T27

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 446837772 4629 0 0
g_div2.Div2Whole_A 446837772 5608 0 0
g_div4.Div4Stepped_A 222662653 4525 0 0
g_div4.Div4Whole_A 222662653 5263 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 446837772 4629 0 0
T1 931870 81 0 0
T2 525480 7 0 0
T3 0 13 0 0
T16 9356 6 0 0
T17 2574 0 0 0
T18 131109 0 0 0
T19 10540 0 0 0
T20 1705 0 0 0
T21 0 6 0 0
T22 0 5 0 0
T25 4204 1 0 0
T26 13140 8 0 0
T27 5958 7 0 0
T108 0 11 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 446837772 5608 0 0
T1 931870 82 0 0
T2 525480 8 0 0
T3 0 17 0 0
T16 9356 6 0 0
T17 2574 0 0 0
T18 131109 0 0 0
T19 10540 0 0 0
T20 1705 0 0 0
T21 0 7 0 0
T22 0 5 0 0
T25 4204 1 0 0
T26 13140 8 0 0
T27 5958 9 0 0
T108 0 11 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222662653 4525 0 0
T1 466684 81 0 0
T2 262761 7 0 0
T3 0 13 0 0
T16 5199 6 0 0
T17 1234 0 0 0
T18 49657 0 0 0
T19 5210 0 0 0
T20 813 0 0 0
T21 0 6 0 0
T22 0 5 0 0
T25 2094 1 0 0
T26 7706 8 0 0
T27 3234 7 0 0
T108 0 11 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222662653 5263 0 0
T1 466684 82 0 0
T2 262761 8 0 0
T3 0 17 0 0
T16 5199 6 0 0
T17 1234 0 0 0
T18 49657 0 0 0
T19 5210 0 0 0
T20 813 0 0 0
T21 0 7 0 0
T22 0 4 0 0
T25 2094 1 0 0
T26 7706 8 0 0
T27 3234 9 0 0
T108 0 11 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T4,T24
10CoveredT26,T27,T1
11CoveredT25,T26,T27

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 446837772 4629 0 0
g_div2.Div2Whole_A 446837772 5608 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 446837772 4629 0 0
T1 931870 81 0 0
T2 525480 7 0 0
T3 0 13 0 0
T16 9356 6 0 0
T17 2574 0 0 0
T18 131109 0 0 0
T19 10540 0 0 0
T20 1705 0 0 0
T21 0 6 0 0
T22 0 5 0 0
T25 4204 1 0 0
T26 13140 8 0 0
T27 5958 7 0 0
T108 0 11 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 446837772 5608 0 0
T1 931870 82 0 0
T2 525480 8 0 0
T3 0 17 0 0
T16 9356 6 0 0
T17 2574 0 0 0
T18 131109 0 0 0
T19 10540 0 0 0
T20 1705 0 0 0
T21 0 7 0 0
T22 0 5 0 0
T25 4204 1 0 0
T26 13140 8 0 0
T27 5958 9 0 0
T108 0 11 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T4,T24
10CoveredT26,T27,T1
11CoveredT25,T26,T27

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 222662653 4525 0 0
g_div4.Div4Whole_A 222662653 5263 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222662653 4525 0 0
T1 466684 81 0 0
T2 262761 7 0 0
T3 0 13 0 0
T16 5199 6 0 0
T17 1234 0 0 0
T18 49657 0 0 0
T19 5210 0 0 0
T20 813 0 0 0
T21 0 6 0 0
T22 0 5 0 0
T25 2094 1 0 0
T26 7706 8 0 0
T27 3234 7 0 0
T108 0 11 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 222662653 5263 0 0
T1 466684 82 0 0
T2 262761 8 0 0
T3 0 17 0 0
T16 5199 6 0 0
T17 1234 0 0 0
T18 49657 0 0 0
T19 5210 0 0 0
T20 813 0 0 0
T21 0 7 0 0
T22 0 4 0 0
T25 2094 1 0 0
T26 7706 8 0 0
T27 3234 9 0 0
T108 0 11 0 0

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