Assert Coverage for Module :
clkmgr_pwrmgr_sva_if
Assertion Details
IoStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
149 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
5 |
0 |
0 |
T46 |
0 |
4 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
2 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T157 |
0 |
1 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |
IoStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
149 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
5 |
0 |
0 |
T46 |
0 |
4 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
2 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T157 |
0 |
1 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |
MainStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
137 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
2 |
0 |
0 |
T39 |
0 |
6 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T157 |
0 |
2 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |
MainStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
137 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
2 |
0 |
0 |
T39 |
0 |
6 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
T156 |
0 |
2 |
0 |
0 |
T157 |
0 |
2 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |
UsbStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
143 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |
UsbStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162507769 |
143 |
0 |
0 |
T37 |
1076 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T73 |
200385 |
0 |
0 |
0 |
T74 |
168997 |
0 |
0 |
0 |
T114 |
19702 |
0 |
0 |
0 |
T115 |
3436 |
0 |
0 |
0 |
T138 |
204528 |
0 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
T156 |
0 |
1 |
0 |
0 |
T158 |
0 |
6 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
188477 |
0 |
0 |
0 |
T162 |
126696 |
0 |
0 |
0 |
T163 |
1230 |
0 |
0 |
0 |
T164 |
1647 |
0 |
0 |
0 |