Module Definition
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Module : clkmgr_pwrmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_pwrmgr_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_pwrmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IoStatusFall_A 162507769 149 0 0
IoStatusRise_A 162507769 149 0 0
MainStatusFall_A 162507769 137 0 0
MainStatusRise_A 162507769 137 0 0
UsbStatusFall_A 162507769 143 0 0
UsbStatusRise_A 162507769 143 0 0


IoStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 149 0 0
T37 1076 3 0 0
T38 0 1 0 0
T39 0 5 0 0
T46 0 4 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 2 0 0
T156 0 2 0 0
T157 0 1 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 4 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

IoStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 149 0 0
T37 1076 3 0 0
T38 0 1 0 0
T39 0 5 0 0
T46 0 4 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 2 0 0
T156 0 2 0 0
T157 0 1 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 4 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

MainStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 137 0 0
T37 1076 3 0 0
T38 0 2 0 0
T39 0 6 0 0
T46 0 5 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 3 0 0
T156 0 2 0 0
T157 0 2 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 5 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

MainStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 137 0 0
T37 1076 3 0 0
T38 0 2 0 0
T39 0 6 0 0
T46 0 5 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 3 0 0
T156 0 2 0 0
T157 0 2 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 5 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

UsbStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 143 0 0
T37 1076 3 0 0
T38 0 1 0 0
T39 0 4 0 0
T40 0 1 0 0
T46 0 3 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 3 0 0
T156 0 1 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 5 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

UsbStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162507769 143 0 0
T37 1076 3 0 0
T38 0 1 0 0
T39 0 4 0 0
T40 0 1 0 0
T46 0 3 0 0
T73 200385 0 0 0
T74 168997 0 0 0
T114 19702 0 0 0
T115 3436 0 0 0
T138 204528 0 0 0
T155 0 3 0 0
T156 0 1 0 0
T158 0 6 0 0
T159 0 4 0 0
T160 0 5 0 0
T161 188477 0 0 0
T162 126696 0 0 0
T163 1230 0 0 0
T164 1647 0 0 0

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