Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48857	0	0
CgEnOn_A	2147483647	39768	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48857	0	0
T1	2612823	380	0	0
T2	1477812	231	0	0
T4	163047	63	0	0
T5	226094	3	0	0
T6	166813	3	0	0
T16	26899	3	0	0
T17	2682	0	0	0
T19	0	7	0	0
T24	4243	4	0	0
T25	11724	3	0	0
T26	38382	3	0	0
T27	17014	3	0	0
T30	2570442	10	0	0
T31	509736	0	0	0
T37	0	15	0	0
T38	0	5	0	0
T39	0	25	0	0
T46	0	20	0	0
T107	187533	0	0	0
T113	483711	0	0	0
T136	1381270	0	0	0
T155	0	10	0	0
T156	0	10	0	0
T157	0	5	0	0
T158	0	30	0	0
T165	0	5	0	0
T166	4422	0	0	0
T167	11233	0	0	0
T168	3571	0	0	0
T169	7574	0	0	0
T170	5667	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39768	0	0
T1	700025	207	0	0
T2	394140	115	0	0
T3	0	36	0	0
T10	0	32	0	0
T12	0	208	0	0
T16	7797	0	0	0
T17	1851	0	0	0
T18	74484	0	0	0
T19	7815	0	0	0
T20	1219	0	0	0
T21	22312	0	0	0
T22	5846	0	0	0
T23	3495	0	0	0
T30	2379268	8	0	0
T31	283165	0	0	0
T37	11826	15	0	0
T38	0	5	0	0
T39	0	25	0	0
T46	0	20	0	0
T78	0	14	0	0
T107	74796	0	0	0
T110	0	2	0	0
T112	0	2	0	0
T113	268661	0	0	0
T136	767464	0	0	0
T155	0	10	0	0
T156	0	10	0	0
T157	0	5	0	0
T158	0	30	0	0
T159	0	4	0	0
T165	0	4	0	0
T166	2435	0	0	0
T167	6432	0	0	0
T168	1991	0	0	0
T169	4171	0	0	0
T170	3120	0	0	0
T171	0	5	0	0
T172	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222662241	161	0	0
CgEnOn_A	222662241	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662241	161	0	0
T30	951712	2	0	0
T31	113266	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	29922	0	0	0
T113	107465	0	0	0
T136	306988	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	974	0	0	0
T167	2574	0	0	0
T168	797	0	0	0
T169	1669	0	0	0
T170	1248	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662241	161	0	0
T30	951712	2	0	0
T31	113266	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	29922	0	0	0
T113	107465	0	0	0
T136	306988	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	974	0	0	0
T167	2574	0	0	0
T168	797	0	0	0
T169	1669	0	0	0
T170	1248	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111330503	161	0	0
CgEnOn_A	111330503	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	446837348	161	0	0
CgEnOn_A	446837348	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837348	161	0	0
T30	191174	2	0	0
T31	226571	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	112737	0	0	0
T113	215050	0	0	0
T136	613806	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	1987	0	0	0
T167	4801	0	0	0
T168	1580	0	0	0
T169	3403	0	0	0
T170	2547	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837348	152	0	0
T37	11826	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T73	354075	0	0	0
T74	107233	0	0	0
T114	18914	0	0	0
T115	21997	0	0	0
T138	768087	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	140445	0	0	0
T162	122515	0	0	0
T163	4925	0	0	0
T164	1582	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	137	0	0
CgEnOn_A	476560808	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	137	0	0
T37	12293	3	0	0
T38	0	2	0	0
T39	0	6	0	0
T46	0	5	0	0
T73	392747	0	0	0
T74	112125	0	0	0
T114	19702	0	0	0
T115	22914	0	0	0
T138	800115	0	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	194300	0	0	0
T162	109624	0	0	0
T163	5131	0	0	0
T164	1647	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	137	0	0
T37	12293	3	0	0
T38	0	2	0	0
T39	0	6	0	0
T46	0	5	0	0
T73	392747	0	0	0
T74	112125	0	0	0
T114	19702	0	0	0
T115	22914	0	0	0
T138	800115	0	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	194300	0	0	0
T162	109624	0	0	0
T163	5131	0	0	0
T164	1647	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111330503	161	0	0
CgEnOn_A	111330503	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	137	0	0
CgEnOn_A	476560808	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	137	0	0
T37	12293	3	0	0
T38	0	2	0	0
T39	0	6	0	0
T46	0	5	0	0
T73	392747	0	0	0
T74	112125	0	0	0
T114	19702	0	0	0
T115	22914	0	0	0
T138	800115	0	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	194300	0	0	0
T162	109624	0	0	0
T163	5131	0	0	0
T164	1647	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	137	0	0
T37	12293	3	0	0
T38	0	2	0	0
T39	0	6	0	0
T46	0	5	0	0
T73	392747	0	0	0
T74	112125	0	0	0
T114	19702	0	0	0
T115	22914	0	0	0
T138	800115	0	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	194300	0	0	0
T162	109624	0	0	0
T163	5131	0	0	0
T164	1647	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111330503	161	0	0
CgEnOn_A	111330503	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	161	0	0
T30	475852	2	0	0
T31	56633	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T46	0	4	0	0
T107	14958	0	0	0
T113	53732	0	0	0
T136	153492	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T165	0	1	0	0
T166	487	0	0	0
T167	1286	0	0	0
T168	398	0	0	0
T169	834	0	0	0
T170	624	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222662241	8031	0	0
CgEnOn_A	222662241	5766	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662241	8031	0	0
T1	466684	112	0	0
T2	262760	66	0	0
T4	29710	21	0	0
T5	64568	1	0	0
T6	47650	1	0	0
T16	5198	1	0	0
T24	716	1	0	0
T25	2094	1	0	0
T26	7705	1	0	0
T27	3234	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222662241	5766	0	0
T1	466684	106	0	0
T2	262760	60	0	0
T3	0	18	0	0
T10	0	15	0	0
T12	0	104	0	0
T16	5198	0	0	0
T17	1234	0	0	0
T18	49656	0	0	0
T19	5210	0	0	0
T20	813	0	0	0
T21	14876	0	0	0
T22	3898	0	0	0
T23	2330	0	0	0
T78	0	7	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	2	0	0
T172	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111330503	7920	0	0
CgEnOn_A	111330503	5655	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	7920	0	0
T1	233341	107	0	0
T2	131380	61	0	0
T4	14855	21	0	0
T5	32284	1	0	0
T6	23825	1	0	0
T16	2599	1	0	0
T24	358	1	0	0
T25	1047	1	0	0
T26	3851	1	0	0
T27	1616	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111330503	5655	0	0
T1	233341	101	0	0
T2	131380	55	0	0
T3	0	18	0	0
T10	0	17	0	0
T12	0	104	0	0
T16	2599	0	0	0
T17	617	0	0	0
T18	24828	0	0	0
T19	2605	0	0	0
T20	406	0	0	0
T21	7436	0	0	0
T22	1948	0	0	0
T23	1165	0	0	0
T78	0	7	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	3	0	0
T172	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	446837348	8043	0	0
CgEnOn_A	446837348	5769	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837348	8043	0	0
T1	931869	105	0	0
T2	525480	61	0	0
T4	118482	21	0	0
T5	129242	1	0	0
T6	95338	1	0	0
T16	9356	1	0	0
T24	1552	1	0	0
T25	4204	1	0	0
T26	13139	1	0	0
T27	5958	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446837348	5769	0	0
T1	931869	99	0	0
T2	525480	55	0	0
T3	0	17	0	0
T10	0	15	0	0
T12	0	105	0	0
T16	9356	0	0	0
T17	2574	0	0	0
T18	131109	0	0	0
T19	10540	0	0	0
T20	1705	0	0	0
T21	27364	0	0	0
T22	6997	0	0	0
T23	4794	0	0	0
T78	0	6	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	3	0	0
T172	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T40
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228923556	7989	0	0
CgEnOn_A	228923556	5713	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228923556	7989	0	0
T1	470853	111	0	0
T2	268224	60	0	0
T4	59244	21	0	0
T5	93426	1	0	0
T6	62072	1	0	0
T16	4678	1	0	0
T24	776	1	0	0
T25	2101	1	0	0
T26	6570	1	0	0
T27	2978	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228923556	5713	0	0
T1	470853	105	0	0
T2	268224	54	0	0
T3	0	18	0	0
T10	0	15	0	0
T12	0	107	0	0
T16	4678	0	0	0
T17	1288	0	0	0
T18	65557	0	0	0
T19	5270	0	0	0
T20	852	0	0	0
T21	13683	0	0	0
T22	3498	0	0	0
T23	2397	0	0	0
T78	0	8	0	0
T110	0	1	0	0
T112	0	1	0	0
T171	0	3	0	0
T172	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T24,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	3928	0	0
CgEnOn_A	476560808	3928	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3928	0	0
T1	980929	56	0	0
T2	558192	43	0	0
T3	0	34	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	7	0	0
T23	0	5	0	0
T24	1617	1	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0
T112	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3928	0	0
T1	980929	56	0	0
T2	558192	43	0	0
T3	0	34	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	7	0	0
T23	0	5	0	0
T24	1617	1	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	14	0	0
T110	0	1	0	0
T111	0	6	0	0
T112	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T24,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	3944	0	0
CgEnOn_A	476560808	3944	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3944	0	0
T1	980929	55	0	0
T2	558192	48	0	0
T3	0	19	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	10	0	0
T23	0	6	0	0
T24	1617	2	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	15	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3944	0	0
T1	980929	55	0	0
T2	558192	48	0	0
T3	0	19	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	10	0	0
T23	0	6	0	0
T24	1617	2	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	15	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T24,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	3931	0	0
CgEnOn_A	476560808	3931	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3931	0	0
T1	980929	56	0	0
T2	558192	48	0	0
T3	0	29	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	2	0	0
T24	1617	2	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3931	0	0
T1	980929	56	0	0
T2	558192	48	0	0
T3	0	29	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	2	0	0
T24	1617	2	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	7	0	0
T112	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T24,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476560808	3992	0	0
CgEnOn_A	476560808	3992	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3992	0	0
T1	980929	57	0	0
T2	558192	46	0	0
T3	0	27	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	8	0	0
T24	1617	1	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	5	0	0
T112	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476560808	3992	0	0
T1	980929	57	0	0
T2	558192	46	0	0
T3	0	27	0	0
T16	9746	0	0	0
T17	2682	0	0	0
T18	136576	0	0	0
T19	10980	11	0	0
T23	0	8	0	0
T24	1617	1	0	0
T25	4379	0	0	0
T26	13687	0	0	0
T27	6206	0	0	0
T78	0	18	0	0
T110	0	1	0	0
T111	0	5	0	0
T112	0	1	0	0