Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	661892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3959043

1

T1

456

T5

13

T15

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133291	1			T1	199		T15	68		T2	27
values[0x0]	1598030	1			T1	390		T5	19		T15	21
values[0x1]	1889614	1			T1	450		T5	18		T15	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357377	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4263558

1

T1

616

T5

15

T15

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18871	1			T1	1		T2	2		T3	164
valid_sources[0x01]	18991	1			T1	8		T16	1		T3	250
valid_sources[0x02]	18981	1			T1	1		T3	267		T81	1
valid_sources[0x03]	18932	1			T1	5		T3	300		T8	2
valid_sources[0x04]	17682	1			T1	9		T2	1		T16	2
valid_sources[0x05]	18839	1			T1	5		T15	1		T2	1
valid_sources[0x06]	17376	1			T1	4		T3	234		T8	18
valid_sources[0x07]	18211	1			T1	5		T5	1		T2	2
valid_sources[0x08]	18455	1			T1	2		T5	2		T2	1
valid_sources[0x09]	19045	1			T1	4		T5	1		T2	2
valid_sources[0x0a]	18758	1			T1	5		T17	4		T3	255
valid_sources[0x0b]	17509	1			T1	6		T5	2		T15	1
valid_sources[0x0c]	17764	1			T1	1		T2	2		T16	1
valid_sources[0x0d]	18816	1			T1	3		T15	1		T2	3
valid_sources[0x0e]	18116	1			T1	5		T3	361		T8	47
valid_sources[0x0f]	17398	1			T1	5		T2	1		T3	209
valid_sources[0x10]	16966	1			T1	7		T15	1		T2	4
valid_sources[0x11]	19644	1			T1	6		T3	260		T8	5
valid_sources[0x12]	17254	1			T1	3		T2	1		T3	211
valid_sources[0x13]	17167	1			T1	1		T15	1		T3	183
valid_sources[0x14]	19798	1			T1	5		T3	326		T8	12
valid_sources[0x15]	17989	1			T1	4		T15	2		T3	259
valid_sources[0x16]	17535	1			T1	4		T15	1		T3	278
valid_sources[0x17]	17538	1			T1	5		T3	209		T8	18
valid_sources[0x18]	17856	1			T1	6		T2	2		T16	3
valid_sources[0x19]	19195	1			T1	2		T5	1		T16	1
valid_sources[0x1a]	17625	1			T1	6		T3	168		T8	4
valid_sources[0x1b]	18159	1			T1	2		T15	1		T2	2
valid_sources[0x1c]	19417	1			T1	1		T15	1		T2	2
valid_sources[0x1d]	18016	1			T1	9		T3	170		T8	6
valid_sources[0x1e]	17852	1			T1	2		T55	2		T3	180
valid_sources[0x1f]	17839	1			T1	7		T5	1		T18	4
valid_sources[0x20]	19606	1			T1	1		T15	3		T3	294
valid_sources[0x21]	18339	1			T1	5		T3	204		T8	12
valid_sources[0x22]	18939	1			T1	4		T3	228		T8	26
valid_sources[0x23]	17367	1			T1	2		T15	1		T3	278
valid_sources[0x24]	18475	1			T1	1		T15	2		T3	282
valid_sources[0x25]	17681	1			T1	8		T15	2		T2	2
valid_sources[0x26]	19360	1			T1	5		T15	1		T3	223
valid_sources[0x27]	19926	1			T1	5		T2	3		T3	278
valid_sources[0x28]	18088	1			T1	7		T16	2		T3	253
valid_sources[0x29]	17846	1			T1	1		T15	1		T3	168
valid_sources[0x2a]	17558	1			T1	7		T2	1		T3	242
valid_sources[0x2b]	18000	1			T1	7		T15	2		T2	3
valid_sources[0x2c]	18947	1			T1	3		T2	3		T3	260
valid_sources[0x2d]	17562	1			T1	6		T15	4		T3	289
valid_sources[0x2e]	17533	1			T1	2		T55	1		T3	233
valid_sources[0x2f]	16318	1			T1	5		T2	2		T55	1
valid_sources[0x30]	16824	1			T1	4		T3	327		T8	11
valid_sources[0x31]	17761	1			T1	2		T2	3		T3	202
valid_sources[0x32]	16624	1			T1	4		T15	1		T16	2
valid_sources[0x33]	19428	1			T1	4		T3	276		T9	5
valid_sources[0x34]	18663	1			T1	6		T2	1		T3	238
valid_sources[0x35]	17810	1			T1	5		T15	1		T17	2
valid_sources[0x36]	17807	1			T1	7		T3	254		T8	20
valid_sources[0x37]	17978	1			T1	4		T5	1		T3	231
valid_sources[0x38]	17634	1			T1	12		T5	1		T15	3
valid_sources[0x39]	18891	1			T1	5		T15	2		T2	5
valid_sources[0x3a]	18463	1			T1	7		T15	2		T3	291
valid_sources[0x3b]	17805	1			T1	4		T5	1		T3	264
valid_sources[0x3c]	17472	1			T1	1		T16	1		T3	285
valid_sources[0x3d]	18256	1			T1	5		T5	1		T2	1
valid_sources[0x3e]	16818	1			T1	2		T2	1		T3	301
valid_sources[0x3f]	17826	1			T1	4		T16	2		T3	259
valid_sources[0x40]	17916	1			T1	3		T5	1		T3	266
valid_sources[0x41]	16955	1			T1	2		T55	1		T3	227
valid_sources[0x42]	18947	1			T1	1		T5	1		T16	1
valid_sources[0x43]	17928	1			T1	3		T15	1		T2	2
valid_sources[0x44]	18600	1			T1	7		T5	1		T15	2
valid_sources[0x45]	17503	1			T1	5		T15	2		T3	240
valid_sources[0x46]	17954	1			T1	3		T2	1		T3	204
valid_sources[0x47]	17879	1			T1	6		T18	1		T3	308
valid_sources[0x48]	16834	1			T1	4		T3	213		T8	4
valid_sources[0x49]	16659	1			T1	1		T2	1		T3	223
valid_sources[0x4a]	19705	1			T1	1		T2	1		T16	2
valid_sources[0x4b]	19220	1			T1	11		T3	193		T8	14
valid_sources[0x4c]	18933	1			T1	9		T3	265		T63	1
valid_sources[0x4d]	16373	1			T1	2		T5	1		T55	1
valid_sources[0x4e]	18504	1			T1	4		T3	235		T9	2
valid_sources[0x4f]	17698	1			T1	4		T3	167		T8	14
valid_sources[0x50]	17515	1			T1	4		T3	271		T8	54
valid_sources[0x51]	18204	1			T1	4		T2	2		T3	199
valid_sources[0x52]	17082	1			T1	6		T3	235		T8	5
valid_sources[0x53]	18658	1			T1	5		T5	1		T55	1
valid_sources[0x54]	17852	1			T1	5		T15	1		T2	1
valid_sources[0x55]	20113	1			T1	8		T15	2		T16	1
valid_sources[0x56]	18479	1			T1	1		T15	1		T17	1
valid_sources[0x57]	17511	1			T1	7		T2	4		T3	376
valid_sources[0x58]	20245	1			T1	3		T2	1		T3	212
valid_sources[0x59]	16605	1			T1	2		T3	250		T8	29
valid_sources[0x5a]	17348	1			T1	7		T2	1		T3	317
valid_sources[0x5b]	18830	1			T1	6		T2	1		T55	1
valid_sources[0x5c]	17403	1			T1	3		T15	2		T3	265
valid_sources[0x5d]	18015	1			T1	7		T15	1		T2	1
valid_sources[0x5e]	17852	1			T1	5		T55	1		T3	289
valid_sources[0x5f]	17406	1			T1	3		T15	1		T3	255
valid_sources[0x60]	18648	1			T1	5		T3	204		T8	31
valid_sources[0x61]	17268	1			T1	7		T3	299		T8	14
valid_sources[0x62]	17547	1			T1	3		T3	171		T9	2
valid_sources[0x63]	16782	1			T1	6		T2	4		T3	232
valid_sources[0x64]	18183	1			T1	5		T3	237		T8	15
valid_sources[0x65]	17721	1			T1	3		T5	1		T3	265
valid_sources[0x66]	17189	1			T1	3		T3	346		T8	9
valid_sources[0x67]	18121	1			T1	7		T5	1		T15	3
valid_sources[0x68]	19311	1			T1	1		T15	2		T3	213
valid_sources[0x69]	18583	1			T1	7		T3	266		T8	18
valid_sources[0x6a]	17509	1			T1	2		T15	2		T3	268
valid_sources[0x6b]	17175	1			T1	2		T3	210		T8	39
valid_sources[0x6c]	18165	1			T1	3		T15	2		T2	1
valid_sources[0x6d]	18036	1			T1	4		T2	1		T3	241
valid_sources[0x6e]	18052	1			T1	8		T15	4		T16	2
valid_sources[0x6f]	16739	1			T1	1		T16	1		T3	244
valid_sources[0x70]	18572	1			T1	2		T15	1		T2	2
valid_sources[0x71]	17241	1			T1	5		T15	1		T3	200
valid_sources[0x72]	19329	1			T1	7		T15	1		T2	1
valid_sources[0x73]	18781	1			T1	4		T5	1		T2	2
valid_sources[0x74]	17662	1			T1	4		T16	3		T3	206
valid_sources[0x75]	17285	1			T1	1		T5	1		T2	1
valid_sources[0x76]	18208	1			T1	2		T55	1		T3	235
valid_sources[0x77]	18140	1			T1	6		T15	1		T3	345
valid_sources[0x78]	17597	1			T1	6		T15	1		T2	3
valid_sources[0x79]	18691	1			T1	2		T2	2		T16	3
valid_sources[0x7a]	18665	1			T1	4		T2	1		T3	324
valid_sources[0x7b]	17434	1			T1	2		T15	1		T16	1
valid_sources[0x7c]	17282	1			T1	3		T3	273		T8	9
valid_sources[0x7d]	16570	1			T1	4		T5	1		T3	176
valid_sources[0x7e]	15835	1			T3	231		T8	29		T63	1
valid_sources[0x7f]	17857	1			T1	3		T16	1		T3	231
valid_sources[0x80]	17356	1			T1	3		T15	2		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

998085

1

T1

90

T15

33

T2

13

values[0x0]

all_enables

biggest_size

1502323

1

T1

231

T5

9

T15

10

values[0x1]

all_enables

biggest_size

1458635

1

T1

135

T5

4

T15

3