Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T19
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T19,T21
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1036230276	14135	0	0
GateOpen_A	1036230276	20246	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036230276	14135	0	0
T1	834328	12	0	0
T2	225718	0	0	0
T3	0	161	0	0
T4	7384	4	0	0
T5	8248	0	0	0
T8	0	38	0	0
T15	9886	0	0	0
T16	6363	0	0	0
T17	3176	0	0	0
T18	7974	0	0	0
T19	6217	19	0	0
T20	6054	0	0	0
T21	0	14	0	0
T64	0	18	0	0
T66	0	4	0	0
T78	0	4	0	0
T157	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1036230276	20246	0	0
T1	834328	20	0	0
T2	225718	0	0	0
T3	0	181	0	0
T4	7384	8	0	0
T5	8248	0	0	0
T15	9886	4	0	0
T16	6363	0	0	0
T17	3176	0	0	0
T18	7974	4	0	0
T19	6217	23	0	0
T20	6054	0	0	0
T21	0	18	0	0
T32	0	4	0	0
T55	0	4	0	0
T157	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T19
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T19,T21
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	114968883	3339	0	0
GateOpen_A	114968883	4865	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968883	3339	0	0
T1	91997	3	0	0
T2	25073	0	0	0
T3	0	39	0	0
T4	803	1	0	0
T5	901	0	0	0
T8	0	9	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	346	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	702	0	0	0
T21	0	3	0	0
T64	0	4	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968883	4865	0	0
T1	91997	5	0	0
T2	25073	0	0	0
T3	0	44	0	0
T4	803	2	0	0
T5	901	0	0	0
T15	1083	1	0	0
T16	680	0	0	0
T17	346	0	0	0
T18	875	1	0	0
T19	679	6	0	0
T20	702	0	0	0
T21	0	4	0	0
T32	0	1	0	0
T55	0	1	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T19
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T19,T21
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	229938648	3584	0	0
GateOpen_A	229938648	5110	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938648	3584	0	0
T1	183993	3	0	0
T2	50146	0	0	0
T3	0	39	0	0
T4	1605	1	0	0
T5	1802	0	0	0
T8	0	9	0	0
T15	2166	0	0	0
T16	1361	0	0	0
T17	691	0	0	0
T18	1750	0	0	0
T19	1358	5	0	0
T20	1404	0	0	0
T21	0	3	0	0
T64	0	5	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938648	5110	0	0
T1	183993	5	0	0
T2	50146	0	0	0
T3	0	44	0	0
T4	1605	2	0	0
T5	1802	0	0	0
T15	2166	1	0	0
T16	1361	0	0	0
T17	691	0	0	0
T18	1750	1	0	0
T19	1358	6	0	0
T20	1404	0	0	0
T21	0	4	0	0
T32	0	1	0	0
T55	0	1	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T19
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T19,T21
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	457385469	3624	0	0
GateOpen_A	457385469	5153	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385469	3624	0	0
T1	366459	3	0	0
T2	100331	0	0	0
T3	0	41	0	0
T4	3317	1	0	0
T5	3697	0	0	0
T8	0	10	0	0
T15	4425	0	0	0
T16	2881	0	0	0
T17	1426	0	0	0
T18	3566	0	0	0
T19	2768	5	0	0
T20	2632	0	0	0
T21	0	3	0	0
T64	0	4	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385469	5153	0	0
T1	366459	5	0	0
T2	100331	0	0	0
T3	0	46	0	0
T4	3317	2	0	0
T5	3697	0	0	0
T15	4425	1	0	0
T16	2881	0	0	0
T17	1426	0	0	0
T18	3566	1	0	0
T19	2768	6	0	0
T20	2632	0	0	0
T21	0	4	0	0
T32	0	1	0	0
T55	0	1	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T19
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T3
1	0	Covered	T4,T19,T21
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233937276	3588	0	0
GateOpen_A	233937276	5118	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233937276	3588	0	0
T1	191879	3	0	0
T2	50168	0	0	0
T3	0	42	0	0
T4	1659	1	0	0
T5	1848	0	0	0
T8	0	10	0	0
T15	2212	0	0	0
T16	1441	0	0	0
T17	713	0	0	0
T18	1783	0	0	0
T19	1412	4	0	0
T20	1316	0	0	0
T21	0	5	0	0
T64	0	5	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233937276	5118	0	0
T1	191879	5	0	0
T2	50168	0	0	0
T3	0	47	0	0
T4	1659	2	0	0
T5	1848	0	0	0
T15	2212	1	0	0
T16	1441	0	0	0
T17	713	0	0	0
T18	1783	1	0	0
T19	1412	5	0	0
T20	1316	0	0	0
T21	0	6	0	0
T32	0	1	0	0
T55	0	1	0	0
T157	0	2	0	0