Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	841128325	79814	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841128325	79814	0	0
T1	572050	109	0	0
T2	261280	136	0	0
T3	0	1154	0	0
T5	9620	0	0	0
T8	0	875	0	0
T9	0	334	0	0
T10	0	783	0	0
T11	0	334	0	0
T12	0	89	0	0
T13	0	40	0	0
T14	0	3153	0	0
T15	11060	0	0	0
T16	14555	0	0	0
T17	7420	0	0	0
T18	4450	0	0	0
T19	6850	0	0	0
T20	12605	0	0	0
T21	6175	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168225665	11627	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	11627	0	0
T1	114410	17	0	0
T2	52256	20	0	0
T3	0	170	0	0
T5	1924	0	0	0
T8	0	122	0	0
T9	0	53	0	0
T10	0	115	0	0
T11	0	50	0	0
T12	0	13	0	0
T13	0	6	0	0
T14	0	465	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168225665	16073	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	16073	0	0
T1	114410	22	0	0
T2	52256	27	0	0
T3	0	230	0	0
T5	1924	0	0	0
T8	0	170	0	0
T9	0	67	0	0
T10	0	158	0	0
T11	0	67	0	0
T12	0	19	0	0
T13	0	8	0	0
T14	0	637	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168225665	24663	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	24663	0	0
T1	114410	31	0	0
T2	52256	41	0	0
T3	0	354	0	0
T5	1924	0	0	0
T8	0	265	0	0
T9	0	93	0	0
T10	0	240	0	0
T11	0	102	0	0
T12	0	29	0	0
T13	0	12	0	0
T14	0	1031	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168225665	11393	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	11393	0	0
T1	114410	18	0	0
T2	52256	20	0	0
T3	0	167	0	0
T5	1924	0	0	0
T8	0	122	0	0
T9	0	54	0	0
T10	0	114	0	0
T11	0	49	0	0
T12	0	11	0	0
T13	0	6	0	0
T14	0	395	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168225665	16058	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	16058	0	0
T1	114410	21	0	0
T2	52256	28	0	0
T3	0	233	0	0
T5	1924	0	0	0
T8	0	196	0	0
T9	0	67	0	0
T10	0	156	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	8	0	0
T14	0	625	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0