Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T16,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	168225665	165580664	0	0
AllClkBypReqTrue_A	168225665	136710	0	0
IoClkBypReqFalse_A	168225665	165501914	0	2415
IoClkBypReqTrue_A	168225665	211042	0	0
LcClkBypAckFalse_A	168225665	165593644	0	0
LcClkBypAckTrue_A	168225665	123730	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	165580664	0	0
T1	114410	113867	0	0
T2	52256	52207	0	0
T4	841	797	0	0
T5	1924	1825	0	0
T15	2212	2103	0	0
T16	2911	2593	0	0
T17	1484	1205	0	0
T18	890	839	0	0
T19	1370	1289	0	0
T20	2521	1961	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	136710	0	0
T1	114410	386	0	0
T2	52256	0	0	0
T3	0	2156	0	0
T5	1924	0	0	0
T8	0	517	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	95	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	325	0	0
T21	1235	0	0	0
T55	0	224	0	0
T61	0	239	0	0
T62	0	98	0	0
T63	0	328	0	0
T65	0	223	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	165501914	0	2415
T1	114410	113722	0	3
T2	52256	52205	0	3
T4	841	795	0	3
T5	1924	1823	0	3
T15	2212	2101	0	3
T16	2911	2589	0	3
T17	1484	1198	0	3
T18	890	837	0	3
T19	1370	1287	0	3
T20	2521	1859	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	211042	0	0
T1	114410	523	0	0
T2	52256	0	0	0
T3	0	3235	0	0
T5	1924	0	0	0
T8	0	756	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	100	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	425	0	0
T21	1235	0	0	0
T32	0	285	0	0
T55	0	477	0	0
T61	0	241	0	0
T62	0	171	0	0
T63	0	334	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	165593644	0	0
T1	114410	113882	0	0
T2	52256	52207	0	0
T4	841	797	0	0
T5	1924	1825	0	0
T15	2212	2103	0	0
T16	2911	2593	0	0
T17	1484	1208	0	0
T18	890	839	0	0
T19	1370	1289	0	0
T20	2521	2033	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	123730	0	0
T1	114410	371	0	0
T2	52256	0	0	0
T3	0	1985	0	0
T5	1924	0	0	0
T8	0	483	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	92	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	253	0	0
T21	1235	0	0	0
T32	0	119	0	0
T55	0	341	0	0
T61	0	162	0	0
T62	0	119	0	0
T63	0	268	0	0