Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1948419328	15493	0	0
TransStop_A	1948419328	7764	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1948419328	15493	0	0
T1	1622968	12	0	0
T2	418056	0	0	0
T3	0	289	0	0
T5	15404	0	0	0
T8	0	75	0	0
T10	0	80	0	0
T15	18436	37	0	0
T16	12004	24	0	0
T17	5940	0	0	0
T18	14856	0	0	0
T19	11748	0	0	0
T20	10964	0	0	0
T21	32128	0	0	0
T66	0	4	0	0
T67	0	42	0	0
T79	0	31	0	0
T103	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1948419328	7764	0	0
T1	1622968	12	0	0
T2	418056	0	0	0
T3	0	147	0	0
T5	15404	0	0	0
T8	0	41	0	0
T10	0	42	0	0
T15	18436	22	0	0
T16	12004	16	0	0
T17	5940	0	0	0
T18	14856	0	0	0
T19	11748	0	0	0
T20	10964	0	0	0
T21	32128	0	0	0
T66	0	4	0	0
T67	0	25	0	0
T79	0	14	0	0
T103	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487104832	3853	0	0
TransStop_A	487104832	1944	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	3853	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	72	0	0
T5	3851	0	0	0
T8	0	18	0	0
T10	0	19	0	0
T15	4609	11	0	0
T16	3001	5	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	11	0	0
T79	0	7	0	0
T103	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	1944	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	37	0	0
T5	3851	0	0	0
T8	0	11	0	0
T10	0	8	0	0
T15	4609	6	0	0
T16	3001	3	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	7	0	0
T79	0	3	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487104832	3885	0	0
TransStop_A	487104832	1937	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	3885	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	78	0	0
T5	3851	0	0	0
T8	0	23	0	0
T10	0	21	0	0
T15	4609	7	0	0
T16	3001	5	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	9	0	0
T79	0	10	0	0
T103	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	1937	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	37	0	0
T5	3851	0	0	0
T8	0	11	0	0
T10	0	11	0	0
T15	4609	4	0	0
T16	3001	4	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	6	0	0
T79	0	6	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487104832	3893	0	0
TransStop_A	487104832	1930	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	3893	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	66	0	0
T5	3851	0	0	0
T8	0	19	0	0
T10	0	17	0	0
T15	4609	8	0	0
T16	3001	8	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	11	0	0
T79	0	8	0	0
T103	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	1930	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	32	0	0
T5	3851	0	0	0
T8	0	12	0	0
T10	0	10	0	0
T15	4609	4	0	0
T16	3001	5	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	5	0	0
T79	0	3	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	487104832	3862	0	0
TransStop_A	487104832	1953	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	3862	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	73	0	0
T5	3851	0	0	0
T8	0	15	0	0
T10	0	23	0	0
T15	4609	11	0	0
T16	3001	6	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	11	0	0
T79	0	6	0	0
T103	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104832	1953	0	0
T1	405742	3	0	0
T2	104514	0	0	0
T3	0	41	0	0
T5	3851	0	0	0
T8	0	7	0	0
T10	0	13	0	0
T15	4609	8	0	0
T16	3001	4	0	0
T17	1485	0	0	0
T18	3714	0	0	0
T19	2937	0	0	0
T20	2741	0	0	0
T21	8032	0	0	0
T66	0	1	0	0
T67	0	7	0	0
T79	0	2	0	0
T103	0	1	0	0