Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169203733	5891520	0	0
clk_enables_rd_A	169203733	32677	0	0
clk_hints_rd_A	169203733	29209	0	0
extclk_ctrl_rd_A	169203733	34202	0	0
extclk_ctrl_regwen_rd_A	169203733	27760	0	0
jitter_enable_rd_A	169203733	40917	0	0
jitter_regwen_rd_A	169203733	30743	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	5891520	0	0
T3	255865	88343	0	0
T8	575577	0	0	0
T10	0	150025	0	0
T14	0	130923	0	0
T23	0	171887	0	0
T25	23891	0	0	0
T29	1138	0	0	0
T30	0	74980	0	0
T56	0	52745	0	0
T57	0	68177	0	0
T58	0	127524	0	0
T59	0	76160	0	0
T60	0	170657	0	0
T61	1418	0	0	0
T62	1799	0	0	0
T63	1821	0	0	0
T64	1179	0	0	0
T65	1560	0	0	0
T66	2055	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	32677	0	0
T1	114410	5	0	0
T2	52256	0	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0
T30	0	3188	0	0
T56	0	2140	0	0
T58	0	5004	0	0
T128	0	2	0	0
T129	0	4	0	0
T130	0	9	0	0
T131	0	1	0	0
T132	0	5543	0	0
T133	0	1620	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	29209	0	0
T1	114410	7	0	0
T2	52256	0	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0
T30	0	2772	0	0
T56	0	1810	0	0
T58	0	4587	0	0
T66	0	8	0	0
T128	0	6	0	0
T129	0	3	0	0
T130	0	1	0	0
T134	0	7	0	0
T135	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	34202	0	0
T1	114410	35	0	0
T2	52256	0	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	10	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0
T24	0	88	0	0
T26	0	18	0	0
T55	0	25	0	0
T63	0	43	0	0
T94	0	121	0	0
T136	0	13	0	0
T137	0	28	0	0
T138	0	29	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	27760	0	0
T26	18096	5	0	0
T27	17804	0	0	0
T28	18629	0	0	0
T30	0	2894	0	0
T56	0	1813	0	0
T58	0	4340	0	0
T82	2012	0	0	0
T94	0	69	0	0
T132	0	5027	0	0
T133	0	1339	0	0
T136	1814	0	0	0
T139	0	1193	0	0
T140	0	48	0	0
T141	0	25	0	0
T142	2488	0	0	0
T143	1880	0	0	0
T144	1261	0	0	0
T145	2559	0	0	0
T146	1775	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	40917	0	0
T1	114410	205	0	0
T2	52256	0	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	0	0	0
T20	2521	0	0	0
T21	1235	0	0	0
T30	0	2944	0	0
T56	0	2386	0	0
T58	0	5802	0	0
T66	0	121	0	0
T128	0	50	0	0
T129	0	107	0	0
T130	0	59	0	0
T134	0	79	0	0
T135	0	52	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169203733	30743	0	0
T30	0	3181	0	0
T56	182204	2104	0	0
T58	0	5414	0	0
T84	1738	0	0	0
T104	35633	0	0	0
T130	2053	0	0	0
T132	0	5354	0	0
T133	0	1457	0	0
T139	0	1353	0	0
T147	0	899	0	0
T148	0	3047	0	0
T149	0	2600	0	0
T150	0	2672	0	0
T151	3075	0	0	0
T152	1016	0	0	0
T153	1820	0	0	0
T154	2467	0	0	0
T155	3469	0	0	0
T156	2587	0	0	0