Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	168225665	132	0	0
IoStatusRise_A	168225665	132	0	0
MainStatusFall_A	168225665	137	0	0
MainStatusRise_A	168225665	137	0	0
UsbStatusFall_A	168225665	137	0	0
UsbStatusRise_A	168225665	137	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	132	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	1	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	5	0	0
T20	2521	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	132	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	1	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	5	0	0
T20	2521	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	137	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	2	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	4	0	0
T20	2521	0	0	0
T21	0	3	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	0	3	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	137	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	2	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	4	0	0
T20	2521	0	0	0
T21	0	3	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	0	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	137	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	1	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	4	0	0
T20	2521	0	0	0
T21	0	5	0	0
T78	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	6	0	0
T160	0	4	0	0
T161	0	1	0	0
T162	0	3	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168225665	137	0	0
T1	114410	0	0	0
T2	52256	0	0	0
T4	841	1	0	0
T5	1924	0	0	0
T15	2212	0	0	0
T16	2911	0	0	0
T17	1484	0	0	0
T18	890	0	0	0
T19	1370	4	0	0
T20	2521	0	0	0
T21	0	5	0	0
T78	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	6	0	0
T160	0	4	0	0
T161	0	1	0	0
T162	0	3	0	0