Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47940	0	0
CgEnOn_A	2147483647	39102	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47940	0	0
T1	4095211	24	0	0
T2	1078495	3	0	0
T3	0	72	0	0
T4	35162	13	0	0
T5	39549	3	0	0
T8	0	18	0	0
T15	47376	14	0	0
T16	30646	11	0	0
T17	15231	3	0	0
T18	38190	3	0	0
T19	29999	47	0	0
T20	28638	3	0	0
T21	0	18	0	0
T66	0	1	0	0
T78	0	5	0	0
T157	0	12	0	0
T158	0	25	0	0
T159	0	20	0	0
T160	0	30	0	0
T161	0	5	0	0
T162	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39102	0	0
T1	4095211	24	0	0
T2	1078495	0	0	0
T3	0	550	0	0
T4	35162	21	0	0
T5	39549	0	0	0
T8	0	122	0	0
T15	47376	37	0	0
T16	30646	24	0	0
T17	15231	0	0	0
T18	38190	0	0	0
T19	29999	68	0	0
T20	28638	0	0	0
T21	0	47	0	0
T64	0	32	0	0
T66	0	8	0	0
T78	0	13	0	0
T157	0	29	0	0
T158	0	29	0	0
T159	0	28	0	0
T160	0	40	0	0
T161	0	7	0	0
T162	0	21	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	229938236	141	0	0
CgEnOn_A	229938236	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938236	141	0	0
T1	183993	0	0	0
T2	50146	0	0	0
T4	1605	1	0	0
T5	1802	0	0	0
T15	2165	0	0	0
T16	1360	0	0	0
T17	691	0	0	0
T18	1750	0	0	0
T19	1358	5	0	0
T20	1404	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938236	141	0	0
T1	183993	0	0	0
T2	50146	0	0	0
T4	1605	1	0	0
T5	1802	0	0	0
T15	2165	0	0	0
T16	1360	0	0	0
T17	691	0	0	0
T18	1750	0	0	0
T19	1358	5	0	0
T20	1404	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114968483	141	0	0
CgEnOn_A	114968483	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457385032	141	0	0
CgEnOn_A	457385032	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385032	141	0	0
T1	366458	0	0	0
T2	100330	0	0	0
T4	3316	1	0	0
T5	3697	0	0	0
T15	4424	0	0	0
T16	2880	0	0	0
T17	1426	0	0	0
T18	3565	0	0	0
T19	2767	5	0	0
T20	2632	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385032	135	0	0
T1	366458	0	0	0
T2	100330	0	0	0
T4	3316	1	0	0
T5	3697	0	0	0
T15	4424	0	0	0
T16	2880	0	0	0
T17	1426	0	0	0
T18	3565	0	0	0
T19	2767	5	0	0
T20	2632	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	141	0	0
CgEnOn_A	487104382	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	141	0	0
T1	405741	0	0	0
T2	104514	0	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T15	4609	0	0	0
T16	3001	0	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T58	0	1	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	138	0	0
T1	405741	0	0	0
T2	104514	0	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T15	4609	0	0	0
T16	3001	0	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114968483	141	0	0
CgEnOn_A	114968483	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	141	0	0
CgEnOn_A	487104382	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	141	0	0
T1	405741	0	0	0
T2	104514	0	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T15	4609	0	0	0
T16	3001	0	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T58	0	1	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	138	0	0
T1	405741	0	0	0
T2	104514	0	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T15	4609	0	0	0
T16	3001	0	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T78	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114968483	141	0	0
CgEnOn_A	114968483	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	141	0	0
T1	91996	0	0	0
T2	25073	0	0	0
T4	802	1	0	0
T5	901	0	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T78	0	1	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T21
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	229938236	7718	0	0
CgEnOn_A	229938236	5518	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938236	7718	0	0
T1	183993	7	0	0
T2	50146	1	0	0
T4	1605	2	0	0
T5	1802	1	0	0
T15	2165	1	0	0
T16	1360	2	0	0
T17	691	1	0	0
T18	1750	1	0	0
T19	1358	6	0	0
T20	1404	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229938236	5518	0	0
T1	183993	3	0	0
T2	50146	0	0	0
T3	0	69	0	0
T4	1605	1	0	0
T5	1802	0	0	0
T8	0	11	0	0
T15	2165	0	0	0
T16	1360	0	0	0
T17	691	0	0	0
T18	1750	0	0	0
T19	1358	5	0	0
T20	1404	0	0	0
T21	0	3	0	0
T64	0	9	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T21
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114968483	7688	0	0
CgEnOn_A	114968483	5488	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	7688	0	0
T1	91996	7	0	0
T2	25073	1	0	0
T4	802	2	0	0
T5	901	1	0	0
T15	1083	1	0	0
T16	680	2	0	0
T17	345	1	0	0
T18	875	1	0	0
T19	679	6	0	0
T20	701	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114968483	5488	0	0
T1	91996	3	0	0
T2	25073	0	0	0
T3	0	65	0	0
T4	802	1	0	0
T5	901	0	0	0
T8	0	12	0	0
T15	1083	0	0	0
T16	680	0	0	0
T17	345	0	0	0
T18	875	0	0	0
T19	679	5	0	0
T20	701	0	0	0
T21	0	3	0	0
T64	0	8	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T21
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457385032	7748	0	0
CgEnOn_A	457385032	5542	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385032	7748	0	0
T1	366458	7	0	0
T2	100330	1	0	0
T4	3316	2	0	0
T5	3697	1	0	0
T15	4424	1	0	0
T16	2880	2	0	0
T17	1426	1	0	0
T18	3565	1	0	0
T19	2767	6	0	0
T20	2632	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457385032	5542	0	0
T1	366458	3	0	0
T2	100330	0	0	0
T3	0	63	0	0
T4	3316	1	0	0
T5	3697	0	0	0
T8	0	12	0	0
T15	4424	0	0	0
T16	2880	0	0	0
T17	1426	0	0	0
T18	3565	0	0	0
T19	2767	5	0	0
T20	2632	0	0	0
T21	0	3	0	0
T64	0	8	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T21
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233936852	7742	0	0
CgEnOn_A	233936852	5534	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233936852	7742	0	0
T1	191879	7	0	0
T2	50167	1	0	0
T4	1658	2	0	0
T5	1847	1	0	0
T15	2212	1	0	0
T16	1440	2	0	0
T17	713	1	0	0
T18	1782	1	0	0
T19	1411	5	0	0
T20	1316	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233936852	5534	0	0
T1	191879	3	0	0
T2	50167	0	0	0
T3	0	64	0	0
T4	1658	1	0	0
T5	1847	0	0	0
T8	0	12	0	0
T15	2212	0	0	0
T16	1440	0	0	0
T17	713	0	0	0
T18	1782	0	0	0
T19	1411	4	0	0
T20	1316	0	0	0
T21	0	5	0	0
T64	0	7	0	0
T66	0	1	0	0
T78	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	3994	0	0
CgEnOn_A	487104382	3991	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	3994	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	72	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	18	0	0
T15	4609	11	0	0
T16	3001	5	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	3991	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	72	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	18	0	0
T15	4609	11	0	0
T16	3001	5	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	4026	0	0
CgEnOn_A	487104382	4023	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4026	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	78	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	23	0	0
T15	4609	7	0	0
T16	3001	5	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4023	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	78	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	23	0	0
T15	4609	7	0	0
T16	3001	5	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	4034	0	0
CgEnOn_A	487104382	4031	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4034	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	66	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	19	0	0
T15	4609	8	0	0
T16	3001	8	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4031	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	66	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	19	0	0
T15	4609	8	0	0
T16	3001	8	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	487104382	4003	0	0
CgEnOn_A	487104382	4000	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4003	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	73	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	15	0	0
T15	4609	11	0	0
T16	3001	6	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487104382	4000	0	0
T1	405741	3	0	0
T2	104514	0	0	0
T3	0	73	0	0
T4	3409	2	0	0
T5	3850	0	0	0
T8	0	15	0	0
T15	4609	11	0	0
T16	3001	6	0	0
T17	1484	0	0	0
T18	3713	0	0	0
T19	2937	4	0	0
T20	2741	0	0	0
T21	0	3	0	0
T66	0	1	0	0
T157	0	2	0	0