Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	917568	0	0
SrcPulseCheck_M	2147483647	915427	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	917568
T1	423290	208
T2	0	7062
T3	0	2674
T4	0	160
T5	128914	94
T7	0	10
T9	0	14602
T10	0	2568
T16	67828	0
T17	14104	0
T18	7176	0
T19	9458	0
T20	11352	0
T21	5138	0
T22	18806	0
T23	9769	0
T26	0	52
T33	0	592
T34	0	110
T46	9978	2
T50	10412	1
T53	4214	0
T54	6700	1
T59	0	428
T107	0	808
T108	15950	1
T109	14866	1
T110	16540	3
T111	24012	2
T112	16108	1
T113	8036	0
T114	5620	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	915427
T1	221652	208
T2	0	7062
T3	0	2674
T4	0	160
T5	85943	94
T7	0	10
T9	0	14602
T10	0	2568
T16	42085	0
T17	4568	0
T18	4274	0
T19	4045	0
T20	6559	0
T21	3073	0
T22	6170	0
T23	5635	0
T26	0	52
T33	0	592
T34	0	110
T46	21126	2
T50	22896	1
T53	1802	0
T54	13552	1
T59	0	428
T107	0	808
T108	7050	1
T109	6170	1
T110	6932	3
T111	10372	2
T112	7156	1
T113	14438	0
T114	2279	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	449622580	24191	0	0
SrcPulseCheck_M	155507539	24191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	449622580	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	19252	6
T7	0	2
T9	0	774
T16	15960	0
T17	3523	0
T18	1524	0
T19	2237	0
T20	2330	0
T21	1074	0
T22	4646	0
T23	1950	0
T26	0	4
T33	0	24
T34	0	22

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	22

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	449622580	29809	0	0
SrcPulseCheck_M	155507539	29824	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	449622580	29809
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	19252	6
T7	0	4
T9	0	785
T16	15960	0
T17	3523	0
T18	1524	0
T19	2237	0
T20	2330	0
T21	1074	0
T22	4646	0
T23	1950	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	29824
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	29798	0	0
SrcPulseCheck_M	449622580	29810	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	29798
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449622580	29810
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	19252	6
T7	0	4
T9	0	785
T16	15960	0
T17	3523	0
T18	1524	0
T19	2237	0
T20	2330	0
T21	1074	0
T22	4646	0
T23	1950	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	224048900	24191	0	0
SrcPulseCheck_M	155507539	24191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	224048900	24191
T1	44148	16
T2	0	320
T3	0	142
T4	0	32
T5	9587	6
T7	0	2
T9	0	774
T16	5509	0
T17	1742	0
T18	716	0
T19	1065	0
T20	1219	0
T21	525	0
T22	2304	0
T23	1085	0
T26	0	4
T33	0	24
T34	0	22

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	22

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	224048900	29830	0	0
SrcPulseCheck_M	155507539	29853	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	224048900	29830
T1	44148	16
T2	0	327
T3	0	142
T4	0	64
T5	9587	6
T7	0	4
T9	0	785
T16	5509	0
T17	1742	0
T18	716	0
T19	1065	0
T20	1219	0
T21	525	0
T22	2304	0
T23	1085	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	29853
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	29830	0	0
SrcPulseCheck_M	224048900	29834	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	29830
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	224048900	29834
T1	44148	16
T2	0	327
T3	0	142
T4	0	64
T5	9587	6
T7	0	4
T9	0	785
T16	5509	0
T17	1742	0
T18	716	0
T19	1065	0
T20	1219	0
T21	525	0
T22	2304	0
T23	1085	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	112023819	24191	0	0
SrcPulseCheck_M	155507539	24191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	112023819	24191
T1	22074	16
T2	0	320
T3	0	142
T4	0	32
T5	4793	6
T7	0	2
T9	0	774
T16	2756	0
T17	871	0
T18	358	0
T19	532	0
T20	608	0
T21	262	0
T22	1152	0
T23	541	0
T26	0	4
T33	0	24
T34	0	22

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	22

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	112023819	29816	0	0
SrcPulseCheck_M	155507539	29840	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	112023819	29816
T1	22074	16
T2	0	327
T3	0	142
T4	0	64
T5	4793	6
T7	0	4
T9	0	785
T16	2756	0
T17	871	0
T18	358	0
T19	532	0
T20	608	0
T21	262	0
T22	1152	0
T23	541	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	29840
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	29813	0	0
SrcPulseCheck_M	112023819	29817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	29813
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	112023819	29817
T1	22074	16
T2	0	327
T3	0	142
T4	0	64
T5	4793	6
T7	0	4
T9	0	785
T16	2756	0
T17	871	0
T18	358	0
T19	532	0
T20	608	0
T21	262	0
T22	1152	0
T23	541	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	479248214	24191	0	0
SrcPulseCheck_M	155507539	24191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	479248214	24191
T1	92048	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	16625	0
T17	3591	0
T18	1589	0
T19	2330	0
T20	2427	0
T21	1109	0
T22	4839	0
T23	2032	0
T26	0	4
T33	0	24
T34	0	22

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	22

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	479248214	29850	0	0
SrcPulseCheck_M	155507539	29865	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	479248214	29850
T1	92048	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	16625	0
T17	3591	0
T18	1589	0
T19	2330	0
T20	2427	0
T21	1109	0
T22	4839	0
T23	2032	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	29865
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	29841	0	0
SrcPulseCheck_M	479248214	29855	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	29841
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479248214	29855
T1	92048	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	16625	0
T17	3591	0
T18	1589	0
T19	2330	0
T20	2427	0
T21	1109	0
T22	4839	0
T23	2032	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	230065272	23784	0	0
SrcPulseCheck_M	155507539	24191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	230065272	23784
T1	44183	16
T2	0	320
T3	0	142
T4	0	16
T5	18266	6
T7	0	1
T9	0	774
T16	7980	0
T17	1787	0
T18	762	0
T19	1118	0
T20	1166	0
T21	532	0
T22	2323	0
T23	974	0
T26	0	4
T33	0	24
T34	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	24191
T1	88362	16
T2	0	320
T3	0	142
T4	0	32
T5	38054	6
T7	0	2
T9	0	774
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	22

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	230065272	29652	0	0
SrcPulseCheck_M	155507539	29805	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	230065272	29652
T1	44183	16
T2	0	327
T3	0	142
T4	0	56
T5	18266	6
T7	0	3
T9	0	785
T16	7980	0
T17	1787	0
T18	762	0
T19	1118	0
T20	1166	0
T21	532	0
T22	2323	0
T23	974	0
T26	0	4
T33	0	24
T34	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	155507539	29805
T1	88362	16
T2	0	327
T3	0	142
T4	0	64
T5	38054	6
T7	0	4
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	29486	0	0
SrcPulseCheck_M	230065272	29695	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	29486
T1	88362	16
T2	0	327
T3	0	142
T4	0	55
T5	38054	6
T7	0	3
T9	0	785
T16	15960	0
T17	893	0
T18	1557	0
T19	1164	0
T20	2330	0
T21	1118	0
T22	1257	0
T23	1991	0
T26	0	4
T33	0	24
T34	0	33

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230065272	29695
T1	44183	16
T2	0	327
T3	0	142
T4	0	59
T5	18266	6
T7	0	3
T9	0	785
T16	7980	0
T17	1787	0
T18	762	0
T19	1118	0
T20	1166	0
T21	532	0
T22	2323	0
T23	974	0
T26	0	4
T33	0	24
T34	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T47,T48,T50
1	0	Covered	T47,T48,T50
1	1	Covered	T115,T116,T117

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T47,T48,T50
1	0	Covered	T115,T116,T117
1	1	Covered	T47,T48,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	40	0	0
SrcPulseCheck_M	449622580	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	40
T47	3918	1
T48	6064	1
T49	5624	3
T50	5206	1
T52	4179	1
T110	8270	2
T111	12006	1
T114	5620	1
T118	14481	1
T119	13622	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449622580	40
T47	15044	1
T48	5939	1
T49	21595	3
T50	23797	1
T52	14860	1
T110	8270	2
T111	12006	1
T114	5395	1
T118	14331	1
T119	52309	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T50,T49,T52
1	0	Covered	T50,T49,T52
1	1	Covered	T110,T115,T116

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T50,T49,T52
1	0	Covered	T110,T115,T116
1	1	Covered	T50,T49,T52

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	40	0	0
SrcPulseCheck_M	449622580	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	40
T49	5624	2
T50	5206	1
T52	4179	1
T110	8270	4
T111	12006	1
T114	5620	1
T115	6722	3
T118	14481	2
T119	13622	2
T120	11022	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449622580	40
T49	21595	2
T50	23797	1
T52	14860	1
T110	8270	4
T111	12006	1
T114	5395	1
T115	6722	3
T118	14331	2
T119	52309	2
T120	21163	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T50,T54
1	0	Covered	T46,T50,T54
1	1	Covered	T110,T113,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T50,T54
1	0	Covered	T110,T113,T114
1	1	Covered	T46,T50,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	32	0	0
SrcPulseCheck_M	224048900	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	32
T46	4989	2
T50	5206	1
T54	3350	1
T108	7975	1
T109	7433	1
T110	8270	3
T111	12006	2
T112	8054	1
T113	4018	5
T114	5620	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	224048900	32
T46	10563	2
T50	11448	1
T54	6776	1
T108	3525	1
T109	3085	1
T110	3466	3
T111	5186	2
T112	3578	1
T113	7219	5
T114	2279	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T50,T54
1	0	Covered	T46,T50,T54
1	1	Covered	T46,T110,T113

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T50,T54
1	0	Covered	T46,T110,T113
1	1	Covered	T46,T50,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	33	0	0
SrcPulseCheck_M	224048900	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	33
T46	4989	2
T50	5206	1
T53	4214	1
T54	3350	2
T108	7975	1
T109	7433	1
T110	8270	2
T111	12006	2
T112	8054	2
T113	4018	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	224048900	33
T46	10563	2
T50	11448	1
T53	1802	1
T54	6776	2
T108	3525	1
T109	3085	1
T110	3466	2
T111	5186	2
T112	3578	2
T113	7219	7

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T49
1	0	Covered	T46,T47,T49
1	1	Covered	T46,T52,T113

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T49
1	0	Covered	T46,T52,T113
1	1	Covered	T46,T47,T49

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	32	0	0
SrcPulseCheck_M	112023819	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	32
T46	4989	2
T47	3918	1
T49	5624	1
T52	4179	2
T108	7975	1
T111	12006	1
T112	8054	1
T113	4018	3
T121	13761	2
T122	10666	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	112023819	32
T46	5284	2
T47	3472	1
T49	4969	1
T52	3526	2
T108	1761	1
T111	2591	1
T112	1791	1
T113	3610	3
T121	14644	2
T122	10748	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T49,T52
1	0	Covered	T46,T49,T52
1	1	Covered	T52,T113,T123

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T49,T52
1	0	Covered	T52,T113,T123
1	1	Covered	T46,T49,T52

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	32	0	0
SrcPulseCheck_M	112023819	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	32
T46	4989	2
T49	5624	1
T52	4179	2
T108	7975	1
T111	12006	1
T113	4018	3
T114	5620	1
T118	14481	1
T121	13761	1
T122	10666	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	112023819	32
T46	5284	2
T49	4969	1
T52	3526	2
T108	1761	1
T111	2591	1
T113	3610	3
T114	1137	1
T118	3205	1
T121	14644	1
T122	10748	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T47,T48
1	1	Covered	T46,T110,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T110,T114
1	1	Covered	T46,T47,T48

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	42	0	0
SrcPulseCheck_M	479248214	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	42
T46	4989	4
T47	3918	1
T48	6064	1
T49	5624	3
T52	4179	1
T53	4214	1
T69	7246	1
T110	8270	5
T112	8054	2
T113	4018	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479248214	42
T46	23756	4
T47	15672	1
T48	6188	1
T49	22497	3
T52	15480	1
T53	4390	1
T69	14788	1
T110	8615	5
T112	8390	2
T113	16074	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T47,T48
1	1	Covered	T46,T53,T110

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T53,T110
1	1	Covered	T46,T47,T48

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	40	0	0
SrcPulseCheck_M	479248214	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	40
T46	4989	5
T47	3918	1
T48	6064	1
T49	5624	1
T52	4179	2
T53	4214	2
T54	3350	1
T69	7246	2
T109	7433	1
T110	8270	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479248214	40
T46	23756	5
T47	15672	1
T48	6188	1
T49	22497	1
T52	15480	2
T53	4390	2
T54	15228	1
T69	14788	2
T109	7433	1
T110	8615	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T48,T49
1	0	Covered	T46,T48,T49
1	1	Covered	T53,T111,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T48,T49
1	0	Covered	T53,T111,T122
1	1	Covered	T46,T48,T49

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	41	0	0
SrcPulseCheck_M	230065272	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	41
T46	4989	2
T48	6064	1
T49	5624	1
T53	4214	3
T67	6776	1
T69	7246	3
T110	8270	1
T111	12006	3
T113	4018	1
T122	10666	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230065272	41
T46	11403	2
T48	2970	1
T49	10798	1
T53	2107	3
T67	11617	1
T69	7098	3
T110	4135	1
T111	6004	3
T113	7716	1
T122	22259	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T48,T53
1	0	Covered	T46,T48,T53
1	1	Covered	T53,T111,T113

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T46,T48,T53
1	0	Covered	T53,T111,T113
1	1	Covered	T46,T48,T53

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	155507539	46	0	0
SrcPulseCheck_M	230065272	46	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	155507539	46
T46	4989	1
T48	6064	1
T53	4214	3
T67	6776	1
T69	7246	1
T110	8270	1
T111	12006	2
T113	4018	3
T121	13761	1
T122	10666	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230065272	46
T46	11403	1
T48	2970	1
T53	2107	3
T67	11617	1
T69	7098	1
T110	4135	1
T111	6004	2
T113	7716	3
T121	30024	1
T122	22259	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	447206114	92863	0	0
SrcPulseCheck_M	18682455	92161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	447206114	92863
T1	88362	40
T2	0	1477
T3	0	511
T5	19252	10
T9	0	2876
T10	0	594
T16	15960	0
T17	3523	0
T18	1524	0
T19	2237	0
T20	2330	0
T21	1074	0
T22	4646	0
T23	1950	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18682455	92161
T1	195	40
T2	0	1477
T3	0	511
T5	53	10
T9	0	2876
T10	0	594
T16	1164	0
T17	260	0
T18	111	0
T19	163	0
T20	170	0
T21	78	0
T22	338	0
T23	142	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	222886692	92290	0	0
SrcPulseCheck_M	18682455	91591	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	222886692	92290
T1	44148	40
T2	0	1477
T3	0	511
T5	9587	10
T9	0	2874
T10	0	594
T16	5509	0
T17	1742	0
T18	716	0
T19	1065	0
T20	1219	0
T21	525	0
T22	2304	0
T23	1085	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18682455	91591
T1	195	40
T2	0	1477
T3	0	511
T5	53	10
T9	0	2874
T10	0	594
T16	1164	0
T17	260	0
T18	111	0
T19	163	0
T20	170	0
T21	78	0
T22	338	0
T23	142	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111442734	91292	0	0
SrcPulseCheck_M	18682455	90601	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111442734	91292
T1	22074	40
T2	0	1477
T3	0	511
T5	4793	10
T9	0	2859
T10	0	594
T16	2756	0
T17	871	0
T18	358	0
T19	532	0
T20	608	0
T21	262	0
T22	1152	0
T23	541	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18682455	90601
T1	195	40
T2	0	1477
T3	0	511
T5	53	10
T9	0	2859
T10	0	594
T16	1164	0
T17	260	0
T18	111	0
T19	163	0
T20	170	0
T21	78	0
T22	338	0
T23	142	0
T26	0	10
T33	0	130
T59	0	107
T107	0	187

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	476730956	111756	0	0
SrcPulseCheck_M	18898418	111541	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	476730956	111756
T1	92048	40
T2	0	1657
T3	0	715
T5	38054	46
T9	0	3649
T10	0	786
T16	16625	0
T17	3591	0
T18	1589	0
T19	2330	0
T20	2427	0
T21	1109	0
T22	4839	0
T23	2032	0
T26	0	10
T33	0	130
T59	0	107
T107	0	247

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18898418	111541
T1	195	40
T2	0	1657
T3	0	715
T5	89	46
T9	0	3649
T10	0	786
T16	1164	0
T17	260	0
T18	111	0
T19	163	0
T20	170	0
T21	78	0
T22	338	0
T23	142	0
T26	0	10
T33	0	130
T59	0	107
T107	0	247

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T5,T1
0	Covered	T6,T5,T1

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	228857014	110716	0	0
SrcPulseCheck_M	18731791	110002	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	228857014	110716
T1	44183	40
T2	0	1654
T3	0	667
T5	18266	46
T9	0	3615
T10	0	786
T16	7980	0
T17	1787	0
T18	762	0
T19	1118	0
T20	1166	0
T21	532	0
T22	2323	0
T23	974	0
T26	0	10
T33	0	190
T59	0	131
T107	0	235

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	18731791	110002
T1	195	40
T2	0	1654
T3	0	667
T5	89	46
T9	0	3616
T10	0	786
T16	1164	0
T17	260	0
T18	111	0
T19	163	0
T20	170	0
T21	78	0
T22	338	0
T23	142	0
T26	0	10
T33	0	190
T59	0	131
T107	0	235

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb