Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1555075390	1385481	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1555075390	269327	0	0
SrcBusyKnown_A	1555075390	1533227600	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555075390	1385481	0	0
T1	883620	1340	0	0
T2	0	27741	0	0
T3	0	12060	0	0
T4	0	3732	0	0
T5	380540	542	0	0
T7	0	236	0	0
T9	0	40064	0	0
T16	159600	0	0	0
T17	8930	0	0	0
T18	15570	0	0	0
T19	11640	0	0	0
T20	23300	0	0	0
T21	11180	0	0	0
T22	12570	0	0	0
T23	19910	0	0	0
T26	0	109	0	0
T33	0	1532	0	0
T34	0	1133	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	581630	580844	0	0
T5	179904	179046	0	0
T6	16322	15806	0	0
T16	97660	45130	0	0
T17	23028	22382	0	0
T18	9898	9152	0	0
T19	14564	13746	0	0
T20	15500	14706	0	0
T21	7004	6696	0	0
T22	30528	29698	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555075390	269327	0	0
T1	883620	160	0	0
T2	0	3235	0	0
T3	0	1420	0	0
T4	0	455	0	0
T5	380540	60	0	0
T7	0	28	0	0
T9	0	7795	0	0
T16	159600	0	0	0
T17	8930	0	0	0
T18	15570	0	0	0
T19	11640	0	0	0
T20	23300	0	0	0
T21	11180	0	0	0
T22	12570	0	0	0
T23	19910	0	0	0
T26	0	40	0	0
T33	0	240	0	0
T34	0	308	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555075390	1533227600	0	0
T1	883620	882280	0	0
T5	380540	378990	0	0
T6	25210	24260	0	0
T16	159600	68680	0	0
T17	8930	8670	0	0
T18	15570	14190	0	0
T19	11640	10870	0	0
T20	23300	21820	0	0
T21	11180	10640	0	0
T22	12570	12210	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	85850	0	0
DstReqKnown_A	449622580	445402625	0	0
SrcAckBusyChk_A	155507539	24191	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	85850	0	0
T1	88362	95	0	0
T2	0	1663	0	0
T3	0	865	0	0
T4	0	161	0	0
T5	38054	33	0	0
T7	0	10	0	0
T9	0	2775	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	101	0	0
T34	0	55	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449622580	445402625	0	0
T1	88362	88228	0	0
T5	19252	19104	0	0
T6	2494	2401	0	0
T16	15960	6868	0	0
T17	3523	3416	0	0
T18	1524	1390	0	0
T19	2237	2088	0	0
T20	2330	2182	0	0
T21	1074	1021	0	0
T22	4646	4511	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	24191	0	0
T1	88362	16	0	0
T2	0	320	0	0
T3	0	142	0	0
T4	0	32	0	0
T5	38054	6	0	0
T7	0	2	0	0
T9	0	774	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	22	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	124920	0	0
DstReqKnown_A	224048900	223001104	0	0
SrcAckBusyChk_A	155507539	24191	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	124920	0	0
T1	88362	136	0	0
T2	0	2710	0	0
T3	0	1253	0	0
T4	0	260	0	0
T5	38054	52	0	0
T7	0	17	0	0
T9	0	3984	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	151	0	0
T34	0	81	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224048900	223001104	0	0
T1	44148	44114	0	0
T5	9587	9552	0	0
T6	1214	1200	0	0
T16	5509	3432	0	0
T17	1742	1708	0	0
T18	716	695	0	0
T19	1065	1044	0	0
T20	1219	1205	0	0
T21	525	511	0	0
T22	2304	2256	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	24191	0	0
T1	88362	16	0	0
T2	0	320	0	0
T3	0	142	0	0
T4	0	32	0	0
T5	38054	6	0	0
T7	0	2	0	0
T9	0	774	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	22	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	199846	0	0
DstReqKnown_A	112023819	111500023	0	0
SrcAckBusyChk_A	155507539	24191	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	199846	0	0
T1	88362	230	0	0
T2	0	4715	0	0
T3	0	2042	0	0
T4	0	456	0	0
T5	38054	90	0	0
T7	0	31	0	0
T9	0	6424	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	14	0	0
T33	0	261	0	0
T34	0	116	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112023819	111500023	0	0
T1	22074	22057	0	0
T5	4793	4776	0	0
T6	607	600	0	0
T16	2756	1719	0	0
T17	871	854	0	0
T18	358	348	0	0
T19	532	522	0	0
T20	608	601	0	0
T21	262	255	0	0
T22	1152	1128	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	24191	0	0
T1	88362	16	0	0
T2	0	320	0	0
T3	0	142	0	0
T4	0	32	0	0
T5	38054	6	0	0
T7	0	2	0	0
T9	0	774	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	22	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	84331	0	0
DstReqKnown_A	479248214	474806723	0	0
SrcAckBusyChk_A	155507539	24191	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	84331	0	0
T1	88362	77	0	0
T2	0	1945	0	0
T3	0	706	0	0
T4	0	159	0	0
T5	38054	38	0	0
T7	0	10	0	0
T9	0	2715	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	101	0	0
T34	0	58	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479248214	474806723	0	0
T1	92048	91907	0	0
T5	38054	37899	0	0
T6	2599	2501	0	0
T16	16625	7129	0	0
T17	3591	3479	0	0
T18	1589	1448	0	0
T19	2330	2175	0	0
T20	2427	2273	0	0
T21	1109	1055	0	0
T22	4839	4698	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	24191	0	0
T1	88362	16	0	0
T2	0	320	0	0
T3	0	142	0	0
T4	0	32	0	0
T5	38054	6	0	0
T7	0	2	0	0
T9	0	774	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	22	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	122994	0	0
DstReqKnown_A	230065272	227935028	0	0
SrcAckBusyChk_A	155507539	23736	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	122994	0	0
T1	88362	129	0	0
T2	0	2693	0	0
T3	0	1155	0	0
T4	0	152	0	0
T5	38054	55	0	0
T7	0	10	0	0
T9	0	3978	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	153	0	0
T34	0	51	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230065272	227935028	0	0
T1	44183	44116	0	0
T5	18266	18192	0	0
T6	1247	1201	0	0
T16	7980	3417	0	0
T17	1787	1734	0	0
T18	762	695	0	0
T19	1118	1044	0	0
T20	1166	1092	0	0
T21	532	506	0	0
T22	2323	2256	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	23736	0	0
T1	88362	16	0	0
T2	0	320	0	0
T3	0	142	0	0
T4	0	16	0	0
T5	38054	6	0	0
T7	0	1	0	0
T9	0	774	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	106563	0	0
DstReqKnown_A	449622580	445402625	0	0
SrcAckBusyChk_A	155507539	29799	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	106563	0	0
T1	88362	96	0	0
T2	0	1703	0	0
T3	0	864	0	0
T4	0	324	0	0
T5	38054	32	0	0
T7	0	20	0	0
T9	0	2811	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	102	0	0
T34	0	113	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449622580	445402625	0	0
T1	88362	88228	0	0
T5	19252	19104	0	0
T6	2494	2401	0	0
T16	15960	6868	0	0
T17	3523	3416	0	0
T18	1524	1390	0	0
T19	2237	2088	0	0
T20	2330	2182	0	0
T21	1074	1021	0	0
T22	4646	4511	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	29799	0	0
T1	88362	16	0	0
T2	0	327	0	0
T3	0	142	0	0
T4	0	64	0	0
T5	38054	6	0	0
T7	0	4	0	0
T9	0	785	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	154609	0	0
DstReqKnown_A	224048900	223001104	0	0
SrcAckBusyChk_A	155507539	29830	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	154609	0	0
T1	88362	137	0	0
T2	0	2767	0	0
T3	0	1221	0	0
T4	0	512	0	0
T5	38054	52	0	0
T7	0	34	0	0
T9	0	4034	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	11	0	0
T33	0	157	0	0
T34	0	160	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224048900	223001104	0	0
T1	44148	44114	0	0
T5	9587	9552	0	0
T6	1214	1200	0	0
T16	5509	3432	0	0
T17	1742	1708	0	0
T18	716	695	0	0
T19	1065	1044	0	0
T20	1219	1205	0	0
T21	525	511	0	0
T22	2304	2256	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	29830	0	0
T1	88362	16	0	0
T2	0	327	0	0
T3	0	142	0	0
T4	0	64	0	0
T5	38054	6	0	0
T7	0	4	0	0
T9	0	785	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	248124	0	0
DstReqKnown_A	112023819	111500023	0	0
SrcAckBusyChk_A	155507539	29816	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	248124	0	0
T1	88362	232	0	0
T2	0	4806	0	0
T3	0	2094	0	0
T4	0	898	0	0
T5	38054	100	0	0
T7	0	54	0	0
T9	0	6538	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	14	0	0
T33	0	252	0	0
T34	0	229	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112023819	111500023	0	0
T1	22074	22057	0	0
T5	4793	4776	0	0
T6	607	600	0	0
T16	2756	1719	0	0
T17	871	854	0	0
T18	358	348	0	0
T19	532	522	0	0
T20	608	601	0	0
T21	262	255	0	0
T22	1152	1128	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	29816	0	0
T1	88362	16	0	0
T2	0	327	0	0
T3	0	142	0	0
T4	0	64	0	0
T5	38054	6	0	0
T7	0	4	0	0
T9	0	785	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	104378	0	0
DstReqKnown_A	479248214	474806723	0	0
SrcAckBusyChk_A	155507539	29841	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	104378	0	0
T1	88362	79	0	0
T2	0	1987	0	0
T3	0	705	0	0
T4	0	316	0	0
T5	38054	38	0	0
T7	0	20	0	0
T9	0	2750	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	100	0	0
T34	0	116	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479248214	474806723	0	0
T1	92048	91907	0	0
T5	38054	37899	0	0
T6	2599	2501	0	0
T16	16625	7129	0	0
T17	3591	3479	0	0
T18	1589	1448	0	0
T19	2330	2175	0	0
T20	2427	2273	0	0
T21	1109	1055	0	0
T22	4839	4698	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	29841	0	0
T1	88362	16	0	0
T2	0	327	0	0
T3	0	142	0	0
T4	0	64	0	0
T5	38054	6	0	0
T7	0	4	0	0
T9	0	785	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155507539	153866	0	0
DstReqKnown_A	230065272	227935028	0	0
SrcAckBusyChk_A	155507539	29541	0	0
SrcBusyKnown_A	155507539	153322760	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153866	0	0
T1	88362	129	0	0
T2	0	2752	0	0
T3	0	1155	0	0
T4	0	494	0	0
T5	38054	52	0	0
T7	0	30	0	0
T9	0	4055	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	10	0	0
T33	0	154	0	0
T34	0	154	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230065272	227935028	0	0
T1	44183	44116	0	0
T5	18266	18192	0	0
T6	1247	1201	0	0
T16	7980	3417	0	0
T17	1787	1734	0	0
T18	762	695	0	0
T19	1118	1044	0	0
T20	1166	1092	0	0
T21	532	506	0	0
T22	2323	2256	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	29541	0	0
T1	88362	16	0	0
T2	0	327	0	0
T3	0	142	0	0
T4	0	55	0	0
T5	38054	6	0	0
T7	0	3	0	0
T9	0	785	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	0	4	0	0
T33	0	24	0	0
T34	0	33	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	153322760	0	0
T1	88362	88228	0	0
T5	38054	37899	0	0
T6	2521	2426	0	0
T16	15960	6868	0	0
T17	893	867	0	0
T18	1557	1419	0	0
T19	1164	1087	0	0
T20	2330	2182	0	0
T21	1118	1064	0	0
T22	1257	1221	0	0