Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	694814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4000071

1

T5

2

T6

7

T7

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1146582	1			T5	5		T6	16		T7	76
values[0x0]	1631585	1			T5	5		T6	6		T7	30
values[0x1]	1916718	1			T5	4		T6	6		T7	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	383350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4311535

1

T5

4

T6

10

T7

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17399	1			T22	3		T2	5		T30	2
valid_sources[0x01]	18778	1			T2	7		T25	3		T33	2
valid_sources[0x02]	18864	1			T22	2		T2	5		T31	1
valid_sources[0x03]	17115	1			T6	1		T7	3		T1	1
valid_sources[0x04]	19130	1			T1	3		T2	5		T30	2
valid_sources[0x05]	17530	1			T20	1		T22	1		T2	7
valid_sources[0x06]	20240	1			T6	1		T7	3		T2	14
valid_sources[0x07]	20317	1			T7	2		T20	1		T2	11
valid_sources[0x08]	18354	1			T7	3		T2	3		T25	4
valid_sources[0x09]	17628	1			T2	8		T25	3		T33	2
valid_sources[0x0a]	18304	1			T22	1		T2	5		T25	2
valid_sources[0x0b]	18783	1			T24	2		T2	4		T25	5
valid_sources[0x0c]	18265	1			T2	6		T25	3		T33	1
valid_sources[0x0d]	16640	1			T5	5		T1	2		T22	1
valid_sources[0x0e]	18127	1			T22	3		T2	8		T25	1
valid_sources[0x0f]	17018	1			T1	1		T2	8		T33	1
valid_sources[0x10]	17317	1			T1	1		T20	1		T22	1
valid_sources[0x11]	19037	1			T7	3		T1	1		T18	98
valid_sources[0x12]	19748	1			T2	8		T25	1		T33	2
valid_sources[0x13]	20792	1			T1	1		T2	3		T33	1
valid_sources[0x14]	19317	1			T2	8		T25	5		T33	4
valid_sources[0x15]	17645	1			T7	1		T1	1		T2	7
valid_sources[0x16]	18449	1			T23	13		T2	2		T25	1
valid_sources[0x17]	18715	1			T2	13		T31	1		T25	4
valid_sources[0x18]	16825	1			T1	3		T22	1		T2	3
valid_sources[0x19]	17847	1			T2	9		T25	1		T33	3
valid_sources[0x1a]	18243	1			T2	1		T25	4		T12	7
valid_sources[0x1b]	18641	1			T7	4		T2	7		T25	1
valid_sources[0x1c]	18668	1			T7	1		T2	8		T27	2
valid_sources[0x1d]	19476	1			T7	2		T2	4		T25	3
valid_sources[0x1e]	18500	1			T1	4		T2	4		T31	1
valid_sources[0x1f]	18110	1			T6	2		T24	12		T2	9
valid_sources[0x20]	18103	1			T1	1		T2	6		T25	3
valid_sources[0x21]	18764	1			T2	8		T30	5		T25	1
valid_sources[0x22]	18220	1			T2	4		T25	3		T33	2
valid_sources[0x23]	18209	1			T4	133		T2	1		T25	2
valid_sources[0x24]	19027	1			T7	1		T1	4		T2	7
valid_sources[0x25]	17252	1			T1	7		T2	2		T25	4
valid_sources[0x26]	17807	1			T2	9		T25	4		T33	2
valid_sources[0x27]	17600	1			T1	1		T2	9		T25	5
valid_sources[0x28]	21188	1			T2	3		T31	1		T33	10
valid_sources[0x29]	17922	1			T1	1		T24	2		T2	11
valid_sources[0x2a]	19827	1			T7	4		T1	2		T2	3
valid_sources[0x2b]	17208	1			T20	1		T2	9		T25	5
valid_sources[0x2c]	17794	1			T1	1		T2	4		T25	2
valid_sources[0x2d]	19226	1			T7	2		T24	9		T2	6
valid_sources[0x2e]	17773	1			T1	2		T2	8		T25	2
valid_sources[0x2f]	18269	1			T2	8		T31	2		T25	4
valid_sources[0x30]	20410	1			T6	1		T7	3		T1	3
valid_sources[0x31]	18498	1			T22	2		T24	2		T2	9
valid_sources[0x32]	17064	1			T22	1		T2	7		T25	5
valid_sources[0x33]	18077	1			T20	1		T2	8		T25	2
valid_sources[0x34]	16571	1			T2	5		T25	1		T33	12
valid_sources[0x35]	17584	1			T22	1		T2	6		T32	3
valid_sources[0x36]	19148	1			T7	4		T1	1		T20	1
valid_sources[0x37]	19245	1			T2	3		T31	1		T25	4
valid_sources[0x38]	18220	1			T1	3		T20	2		T2	2
valid_sources[0x39]	17423	1			T22	1		T2	4		T25	2
valid_sources[0x3a]	19505	1			T1	2		T2	5		T25	4
valid_sources[0x3b]	18818	1			T2	11		T25	4		T33	1
valid_sources[0x3c]	18230	1			T2	10		T25	2		T33	7
valid_sources[0x3d]	17499	1			T1	1		T2	14		T31	1
valid_sources[0x3e]	17970	1			T2	10		T25	1		T33	4
valid_sources[0x3f]	18033	1			T2	3		T25	3		T33	5
valid_sources[0x40]	19985	1			T1	4		T2	11		T25	5
valid_sources[0x41]	18486	1			T7	1		T2	3		T25	5
valid_sources[0x42]	17964	1			T6	1		T2	8		T25	4
valid_sources[0x43]	19557	1			T1	1		T2	10		T25	2
valid_sources[0x44]	18346	1			T20	1		T2	11		T25	2
valid_sources[0x45]	17619	1			T2	4		T25	2		T33	1
valid_sources[0x46]	17449	1			T1	1		T2	10		T25	2
valid_sources[0x47]	18052	1			T7	1		T2	7		T25	7
valid_sources[0x48]	18819	1			T7	1		T22	1		T2	6
valid_sources[0x49]	18102	1			T2	12		T25	1		T33	2
valid_sources[0x4a]	18443	1			T22	1		T2	4		T25	4
valid_sources[0x4b]	18830	1			T1	2		T2	5		T25	4
valid_sources[0x4c]	18864	1			T22	1		T2	3		T25	5
valid_sources[0x4d]	18453	1			T22	1		T2	3		T25	3
valid_sources[0x4e]	17352	1			T24	11		T2	7		T25	4
valid_sources[0x4f]	17105	1			T2	5		T25	3		T33	1
valid_sources[0x50]	17347	1			T7	2		T1	2		T2	8
valid_sources[0x51]	18135	1			T2	6		T25	6		T12	6
valid_sources[0x52]	18214	1			T7	1		T2	8		T25	2
valid_sources[0x53]	17348	1			T24	5		T2	8		T25	1
valid_sources[0x54]	20262	1			T20	1		T22	1		T25	5
valid_sources[0x55]	18988	1			T7	4		T22	1		T2	3
valid_sources[0x56]	18536	1			T22	1		T2	9		T32	2
valid_sources[0x57]	17442	1			T7	1		T2	4		T30	4
valid_sources[0x58]	17975	1			T1	1		T2	7		T31	1
valid_sources[0x59]	17585	1			T1	1		T2	8		T25	5
valid_sources[0x5a]	16996	1			T2	9		T25	5		T33	2
valid_sources[0x5b]	19471	1			T7	2		T22	1		T2	5
valid_sources[0x5c]	18167	1			T6	1		T2	6		T25	2
valid_sources[0x5d]	17444	1			T2	3		T25	1		T33	1
valid_sources[0x5e]	18093	1			T6	1		T1	3		T22	1
valid_sources[0x5f]	18632	1			T22	1		T2	1		T25	4
valid_sources[0x60]	17851	1			T2	4		T27	1		T31	1
valid_sources[0x61]	17643	1			T22	2		T2	6		T25	7
valid_sources[0x62]	18073	1			T7	2		T22	2		T2	13
valid_sources[0x63]	18199	1			T7	2		T2	10		T32	1
valid_sources[0x64]	18186	1			T1	2		T2	1		T31	1
valid_sources[0x65]	17287	1			T20	1		T21	10		T2	2
valid_sources[0x66]	18189	1			T2	12		T25	2		T33	1
valid_sources[0x67]	17795	1			T22	2		T2	6		T25	2
valid_sources[0x68]	17686	1			T22	1		T30	4		T25	3
valid_sources[0x69]	17507	1			T20	1		T2	8		T25	3
valid_sources[0x6a]	18003	1			T22	1		T2	2		T25	1
valid_sources[0x6b]	18357	1			T1	1		T22	1		T2	6
valid_sources[0x6c]	17779	1			T6	1		T7	2		T1	2
valid_sources[0x6d]	18748	1			T2	5		T25	1		T33	4
valid_sources[0x6e]	16865	1			T7	4		T1	1		T20	1
valid_sources[0x6f]	19214	1			T7	3		T22	1		T2	4
valid_sources[0x70]	18640	1			T1	2		T21	4		T2	2
valid_sources[0x71]	17685	1			T1	3		T22	2		T2	2
valid_sources[0x72]	19924	1			T2	4		T25	1		T33	1
valid_sources[0x73]	19056	1			T7	3		T2	8		T25	4
valid_sources[0x74]	17831	1			T1	2		T22	1		T2	3
valid_sources[0x75]	17981	1			T7	1		T20	2		T2	6
valid_sources[0x76]	18231	1			T2	7		T32	8		T25	3
valid_sources[0x77]	17545	1			T2	6		T32	13		T33	2
valid_sources[0x78]	17787	1			T22	1		T2	4		T30	22
valid_sources[0x79]	17869	1			T22	1		T2	5		T25	5
valid_sources[0x7a]	18543	1			T22	1		T2	7		T25	2
valid_sources[0x7b]	17226	1			T20	1		T31	1		T25	4
valid_sources[0x7c]	17696	1			T6	1		T1	9		T22	1
valid_sources[0x7d]	18180	1			T2	3		T25	7		T33	1
valid_sources[0x7e]	17658	1			T22	1		T2	10		T25	6
valid_sources[0x7f]	18462	1			T1	2		T2	5		T25	3
valid_sources[0x80]	18629	1			T22	1		T2	7		T25	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1006639

1

T5

2

T6

5

T7

32

values[0x0]

all_enables

biggest_size

1524022

1

T6

1

T7

15

T1

44

values[0x1]

all_enables

biggest_size

1469410

1

T6

1

T7

3

T1

28