Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T2
0	1	Covered	T20,T2,T11
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T2
1	0	Covered	T29,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1263178557	15876	0	0
GateOpen_A	1263178557	23045	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263178557	15876	0	0
T2	1113064	44	0	0
T4	158654	0	0	0
T11	0	20	0	0
T12	0	60	0	0
T13	0	206	0	0
T20	4138	13	0	0
T21	3869	0	0	0
T22	18237	0	0	0
T23	8577	0	0	0
T24	83040	0	0	0
T27	7929	0	0	0
T28	10017	0	0	0
T29	3146	13	0	0
T39	0	11	0	0
T58	0	4	0	0
T59	0	9	0	0
T132	0	17	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263178557	23045	0	0
T1	226475	0	0	0
T2	0	64	0	0
T4	158654	0	0	0
T5	3466	4	0	0
T6	10545	4	0	0
T7	28640	0	0	0
T18	6684	4	0	0
T19	11234	4	0	0
T20	4138	13	0	0
T21	3869	4	0	0
T22	18237	4	0	0
T23	0	4	0	0
T24	0	404	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T2
0	1	Covered	T20,T2,T11
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T2
1	0	Covered	T29,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	139504485	3812	0	0
GateOpen_A	139504485	5602	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504485	3812	0	0
T2	119191	11	0	0
T4	18253	0	0	0
T11	0	5	0	0
T12	0	14	0	0
T13	0	53	0	0
T20	438	3	0	0
T21	451	0	0	0
T22	2020	0	0	0
T23	971	0	0	0
T24	7863	0	0	0
T27	866	0	0	0
T28	1109	0	0	0
T29	328	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T132	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504485	5602	0	0
T1	25160	0	0	0
T2	0	16	0	0
T4	18253	0	0	0
T5	389	1	0	0
T6	1152	1	0	0
T7	3167	0	0	0
T18	730	1	0	0
T19	1240	1	0	0
T20	438	3	0	0
T21	451	1	0	0
T22	2020	1	0	0
T23	0	1	0	0
T24	0	101	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T2
0	1	Covered	T20,T2,T11
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T2
1	0	Covered	T29,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	279009990	4029	0	0
GateOpen_A	279009990	5819	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	4029	0	0
T2	238386	12	0	0
T4	36505	0	0	0
T11	0	5	0	0
T12	0	15	0	0
T13	0	51	0	0
T20	875	3	0	0
T21	902	0	0	0
T22	4040	0	0	0
T23	1943	0	0	0
T24	15723	0	0	0
T27	1731	0	0	0
T28	2218	0	0	0
T29	655	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T132	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	5819	0	0
T1	50319	0	0	0
T2	0	17	0	0
T4	36505	0	0	0
T5	778	1	0	0
T6	2303	1	0	0
T7	6333	0	0	0
T18	1459	1	0	0
T19	2479	1	0	0
T20	875	3	0	0
T21	902	1	0	0
T22	4040	1	0	0
T23	0	1	0	0
T24	0	101	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T2
0	1	Covered	T20,T2,T11
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T2
1	0	Covered	T29,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	558718359	3996	0	0
GateOpen_A	558718359	5790	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	3996	0	0
T2	476770	11	0	0
T4	73103	0	0	0
T11	0	5	0	0
T12	0	15	0	0
T13	0	53	0	0
T20	1883	4	0	0
T21	1677	0	0	0
T22	8118	0	0	0
T23	3775	0	0	0
T24	39635	0	0	0
T27	3554	0	0	0
T28	4460	0	0	0
T29	1415	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	3	0	0
T132	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	5790	0	0
T1	100663	0	0	0
T2	0	16	0	0
T4	73103	0	0	0
T5	1533	1	0	0
T6	4726	1	0	0
T7	12760	0	0	0
T18	2997	1	0	0
T19	5010	1	0	0
T20	1883	4	0	0
T21	1677	1	0	0
T22	8118	1	0	0
T23	0	1	0	0
T24	0	101	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T2
0	1	Covered	T20,T2,T11
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T2
1	0	Covered	T29,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	285945723	4039	0	0
GateOpen_A	285945723	5834	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945723	4039	0	0
T2	278717	10	0	0
T4	30793	0	0	0
T11	0	5	0	0
T12	0	16	0	0
T13	0	49	0	0
T20	942	3	0	0
T21	839	0	0	0
T22	4059	0	0	0
T23	1888	0	0	0
T24	19819	0	0	0
T27	1778	0	0	0
T28	2230	0	0	0
T29	748	4	0	0
T39	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T132	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945723	5834	0	0
T1	50333	0	0	0
T2	0	15	0	0
T4	30793	0	0	0
T5	766	1	0	0
T6	2364	1	0	0
T7	6380	0	0	0
T18	1498	1	0	0
T19	2505	1	0	0
T20	942	3	0	0
T21	839	1	0	0
T22	4059	1	0	0
T23	0	1	0	0
T24	0	101	0	0