Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	870540315	75182	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870540315	75182	0	0
T1	41940	42	0	0
T2	2902230	211	0	0
T3	0	135	0	0
T4	91375	0	0	0
T11	0	341	0	0
T12	0	284	0	0
T13	0	1300	0	0
T14	0	430	0	0
T15	0	62	0	0
T16	0	814	0	0
T17	0	111	0	0
T18	15605	0	0	0
T19	6000	0	0	0
T20	9410	0	0	0
T21	8380	0	0	0
T22	8450	0	0	0
T23	6490	0	0	0
T24	99095	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174108063	11309	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	11309	0	0
T1	8388	8	0	0
T2	580446	31	0	0
T3	0	22	0	0
T4	18275	0	0	0
T11	0	53	0	0
T12	0	56	0	0
T13	0	171	0	0
T14	0	70	0	0
T15	0	9	0	0
T16	0	119	0	0
T17	0	15	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174108063	11147	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	11147	0	0
T1	8388	8	0	0
T2	580446	27	0	0
T3	0	22	0	0
T4	18275	0	0	0
T11	0	51	0	0
T12	0	56	0	0
T13	0	167	0	0
T14	0	70	0	0
T15	0	9	0	0
T16	0	102	0	0
T17	0	15	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174108063	15211	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	15211	0	0
T1	8388	8	0	0
T2	580446	40	0	0
T3	0	27	0	0
T4	18275	0	0	0
T11	0	68	0	0
T12	0	56	0	0
T13	0	262	0	0
T14	0	86	0	0
T15	0	14	0	0
T16	0	162	0	0
T17	0	23	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174108063	15060	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	15060	0	0
T1	8388	8	0	0
T2	580446	42	0	0
T3	0	27	0	0
T4	18275	0	0	0
T11	0	66	0	0
T12	0	56	0	0
T13	0	264	0	0
T14	0	87	0	0
T15	0	12	0	0
T16	0	164	0	0
T17	0	22	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174108063	22455	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	22455	0	0
T1	8388	10	0	0
T2	580446	71	0	0
T3	0	37	0	0
T4	18275	0	0	0
T11	0	103	0	0
T12	0	60	0	0
T13	0	436	0	0
T14	0	117	0	0
T15	0	18	0	0
T16	0	267	0	0
T17	0	36	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0