Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1388307 |
1387556 |
0 |
0 |
T4 |
1010953 |
1007934 |
0 |
0 |
T5 |
41046 |
39106 |
0 |
0 |
T6 |
76101 |
73537 |
0 |
0 |
T7 |
205661 |
202643 |
0 |
0 |
T18 |
81463 |
77725 |
0 |
0 |
T19 |
80004 |
78349 |
0 |
0 |
T20 |
50013 |
45890 |
0 |
0 |
T21 |
44721 |
42750 |
0 |
0 |
T22 |
126118 |
124532 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044648378 |
1028329086 |
0 |
14490 |
T1 |
50328 |
50280 |
0 |
18 |
T4 |
109650 |
109308 |
0 |
18 |
T5 |
9294 |
8790 |
0 |
18 |
T6 |
7086 |
6804 |
0 |
18 |
T7 |
19134 |
18792 |
0 |
18 |
T18 |
18726 |
17784 |
0 |
18 |
T19 |
7200 |
7014 |
0 |
18 |
T20 |
11292 |
10302 |
0 |
18 |
T21 |
10056 |
9558 |
0 |
18 |
T22 |
10140 |
9972 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
536878 |
536505 |
0 |
21 |
T4 |
342252 |
341002 |
0 |
21 |
T5 |
11014 |
10420 |
0 |
21 |
T6 |
26776 |
25759 |
0 |
21 |
T7 |
72301 |
71051 |
0 |
21 |
T18 |
21723 |
20630 |
0 |
21 |
T19 |
28282 |
27580 |
0 |
21 |
T20 |
13490 |
12307 |
0 |
21 |
T21 |
12012 |
11415 |
0 |
21 |
T22 |
45322 |
44622 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
219488 |
0 |
0 |
T1 |
536878 |
4 |
0 |
0 |
T2 |
0 |
237 |
0 |
0 |
T4 |
342252 |
4 |
0 |
0 |
T5 |
11014 |
43 |
0 |
0 |
T6 |
26776 |
40 |
0 |
0 |
T7 |
72301 |
160 |
0 |
0 |
T11 |
0 |
323 |
0 |
0 |
T12 |
0 |
296 |
0 |
0 |
T13 |
0 |
24 |
0 |
0 |
T18 |
21723 |
193 |
0 |
0 |
T19 |
28282 |
12 |
0 |
0 |
T20 |
13490 |
43 |
0 |
0 |
T21 |
12012 |
95 |
0 |
0 |
T22 |
45322 |
88 |
0 |
0 |
T23 |
0 |
22 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T30 |
0 |
103 |
0 |
0 |
T31 |
0 |
74 |
0 |
0 |
T100 |
0 |
92 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
801101 |
800732 |
0 |
0 |
T4 |
559051 |
557585 |
0 |
0 |
T5 |
20738 |
19857 |
0 |
0 |
T6 |
42239 |
40935 |
0 |
0 |
T7 |
114226 |
112761 |
0 |
0 |
T18 |
41014 |
39272 |
0 |
0 |
T19 |
44522 |
43716 |
0 |
0 |
T20 |
25231 |
23242 |
0 |
0 |
T21 |
22653 |
21738 |
0 |
0 |
T22 |
70656 |
69899 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558717927 |
554019293 |
0 |
0 |
T1 |
100662 |
100596 |
0 |
0 |
T4 |
73102 |
72885 |
0 |
0 |
T5 |
1532 |
1453 |
0 |
0 |
T6 |
4726 |
4550 |
0 |
0 |
T7 |
12759 |
12542 |
0 |
0 |
T18 |
2997 |
2849 |
0 |
0 |
T19 |
5010 |
4889 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
8118 |
7997 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558717927 |
554011931 |
0 |
2415 |
T1 |
100662 |
100593 |
0 |
3 |
T4 |
73102 |
72882 |
0 |
3 |
T5 |
1532 |
1450 |
0 |
3 |
T6 |
4726 |
4547 |
0 |
3 |
T7 |
12759 |
12539 |
0 |
3 |
T18 |
2997 |
2846 |
0 |
3 |
T19 |
5010 |
4886 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
8118 |
7994 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558717927 |
31673 |
0 |
0 |
T1 |
100662 |
0 |
0 |
0 |
T2 |
0 |
102 |
0 |
0 |
T4 |
73102 |
0 |
0 |
0 |
T5 |
1532 |
9 |
0 |
0 |
T6 |
4726 |
0 |
0 |
0 |
T7 |
12759 |
0 |
0 |
0 |
T11 |
0 |
131 |
0 |
0 |
T12 |
0 |
131 |
0 |
0 |
T18 |
2997 |
0 |
0 |
0 |
T19 |
5010 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
16 |
0 |
0 |
T22 |
8118 |
0 |
0 |
0 |
T23 |
0 |
11 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T30 |
0 |
49 |
0 |
0 |
T31 |
0 |
31 |
0 |
0 |
T100 |
0 |
50 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
19847 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
55 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
15 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
96 |
0 |
0 |
T12 |
0 |
66 |
0 |
0 |
T13 |
0 |
24 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
21 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T30 |
0 |
7 |
0 |
0 |
T31 |
0 |
26 |
0 |
0 |
T100 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T21,T23 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T21,T23 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
22413 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
80 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
9 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
96 |
0 |
0 |
T12 |
0 |
99 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
26 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T30 |
0 |
47 |
0 |
0 |
T31 |
0 |
17 |
0 |
0 |
T100 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
593248743 |
0 |
0 |
T1 |
104860 |
104834 |
0 |
0 |
T4 |
58150 |
58053 |
0 |
0 |
T5 |
1596 |
1570 |
0 |
0 |
T6 |
4922 |
4796 |
0 |
0 |
T7 |
13291 |
13194 |
0 |
0 |
T18 |
3121 |
3038 |
0 |
0 |
T19 |
5218 |
5163 |
0 |
0 |
T20 |
1961 |
1821 |
0 |
0 |
T21 |
1746 |
1705 |
0 |
0 |
T22 |
8456 |
8415 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
593248743 |
0 |
0 |
T1 |
104860 |
104834 |
0 |
0 |
T4 |
58150 |
58053 |
0 |
0 |
T5 |
1596 |
1570 |
0 |
0 |
T6 |
4922 |
4796 |
0 |
0 |
T7 |
13291 |
13194 |
0 |
0 |
T18 |
3121 |
3038 |
0 |
0 |
T19 |
5218 |
5163 |
0 |
0 |
T20 |
1961 |
1821 |
0 |
0 |
T21 |
1746 |
1705 |
0 |
0 |
T22 |
8456 |
8415 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558717927 |
556349902 |
0 |
0 |
T1 |
100662 |
100637 |
0 |
0 |
T4 |
73102 |
73008 |
0 |
0 |
T5 |
1532 |
1507 |
0 |
0 |
T6 |
4726 |
4605 |
0 |
0 |
T7 |
12759 |
12665 |
0 |
0 |
T18 |
2997 |
2917 |
0 |
0 |
T19 |
5010 |
4957 |
0 |
0 |
T20 |
1882 |
1748 |
0 |
0 |
T21 |
1676 |
1637 |
0 |
0 |
T22 |
8118 |
8079 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558717927 |
556349902 |
0 |
0 |
T1 |
100662 |
100637 |
0 |
0 |
T4 |
73102 |
73008 |
0 |
0 |
T5 |
1532 |
1507 |
0 |
0 |
T6 |
4726 |
4605 |
0 |
0 |
T7 |
12759 |
12665 |
0 |
0 |
T18 |
2997 |
2917 |
0 |
0 |
T19 |
5010 |
4957 |
0 |
0 |
T20 |
1882 |
1748 |
0 |
0 |
T21 |
1676 |
1637 |
0 |
0 |
T22 |
8118 |
8079 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
279009589 |
279009589 |
0 |
0 |
T1 |
50319 |
50319 |
0 |
0 |
T4 |
36504 |
36504 |
0 |
0 |
T5 |
778 |
778 |
0 |
0 |
T6 |
2303 |
2303 |
0 |
0 |
T7 |
6333 |
6333 |
0 |
0 |
T18 |
1459 |
1459 |
0 |
0 |
T19 |
2479 |
2479 |
0 |
0 |
T20 |
874 |
874 |
0 |
0 |
T21 |
902 |
902 |
0 |
0 |
T22 |
4040 |
4040 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
279009589 |
279009589 |
0 |
0 |
T1 |
50319 |
50319 |
0 |
0 |
T4 |
36504 |
36504 |
0 |
0 |
T5 |
778 |
778 |
0 |
0 |
T6 |
2303 |
2303 |
0 |
0 |
T7 |
6333 |
6333 |
0 |
0 |
T18 |
1459 |
1459 |
0 |
0 |
T19 |
2479 |
2479 |
0 |
0 |
T20 |
874 |
874 |
0 |
0 |
T21 |
902 |
902 |
0 |
0 |
T22 |
4040 |
4040 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
139504068 |
139504068 |
0 |
0 |
T1 |
25159 |
25159 |
0 |
0 |
T4 |
18252 |
18252 |
0 |
0 |
T5 |
388 |
388 |
0 |
0 |
T6 |
1151 |
1151 |
0 |
0 |
T7 |
3166 |
3166 |
0 |
0 |
T18 |
729 |
729 |
0 |
0 |
T19 |
1239 |
1239 |
0 |
0 |
T20 |
437 |
437 |
0 |
0 |
T21 |
451 |
451 |
0 |
0 |
T22 |
2020 |
2020 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
139504068 |
139504068 |
0 |
0 |
T1 |
25159 |
25159 |
0 |
0 |
T4 |
18252 |
18252 |
0 |
0 |
T5 |
388 |
388 |
0 |
0 |
T6 |
1151 |
1151 |
0 |
0 |
T7 |
3166 |
3166 |
0 |
0 |
T18 |
729 |
729 |
0 |
0 |
T19 |
1239 |
1239 |
0 |
0 |
T20 |
437 |
437 |
0 |
0 |
T21 |
451 |
451 |
0 |
0 |
T22 |
2020 |
2020 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
285945322 |
284749929 |
0 |
0 |
T1 |
50333 |
50321 |
0 |
0 |
T4 |
30793 |
30746 |
0 |
0 |
T5 |
766 |
754 |
0 |
0 |
T6 |
2363 |
2302 |
0 |
0 |
T7 |
6379 |
6333 |
0 |
0 |
T18 |
1498 |
1459 |
0 |
0 |
T19 |
2504 |
2478 |
0 |
0 |
T20 |
941 |
874 |
0 |
0 |
T21 |
838 |
819 |
0 |
0 |
T22 |
4058 |
4039 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
285945322 |
284749929 |
0 |
0 |
T1 |
50333 |
50321 |
0 |
0 |
T4 |
30793 |
30746 |
0 |
0 |
T5 |
766 |
754 |
0 |
0 |
T6 |
2363 |
2302 |
0 |
0 |
T7 |
6379 |
6333 |
0 |
0 |
T18 |
1498 |
1459 |
0 |
0 |
T19 |
2504 |
2478 |
0 |
0 |
T20 |
941 |
874 |
0 |
0 |
T21 |
838 |
819 |
0 |
0 |
T22 |
4058 |
4039 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171388181 |
0 |
2415 |
T1 |
8388 |
8380 |
0 |
3 |
T4 |
18275 |
18218 |
0 |
3 |
T5 |
1549 |
1465 |
0 |
3 |
T6 |
1181 |
1134 |
0 |
3 |
T7 |
3189 |
3132 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
1200 |
1169 |
0 |
3 |
T20 |
1882 |
1717 |
0 |
3 |
T21 |
1676 |
1593 |
0 |
3 |
T22 |
1690 |
1662 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
171395822 |
0 |
0 |
T1 |
8388 |
8383 |
0 |
0 |
T4 |
18275 |
18221 |
0 |
0 |
T5 |
1549 |
1468 |
0 |
0 |
T6 |
1181 |
1137 |
0 |
0 |
T7 |
3189 |
3135 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
1200 |
1172 |
0 |
0 |
T20 |
1882 |
1720 |
0 |
0 |
T21 |
1676 |
1596 |
0 |
0 |
T22 |
1690 |
1665 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590773699 |
0 |
2415 |
T1 |
104860 |
104788 |
0 |
3 |
T4 |
58150 |
57921 |
0 |
3 |
T5 |
1596 |
1510 |
0 |
3 |
T6 |
4922 |
4736 |
0 |
3 |
T7 |
13291 |
13062 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
5218 |
5089 |
0 |
3 |
T20 |
1961 |
1789 |
0 |
3 |
T21 |
1746 |
1659 |
0 |
3 |
T22 |
8456 |
8326 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
36270 |
0 |
0 |
T1 |
104860 |
1 |
0 |
0 |
T4 |
58150 |
1 |
0 |
0 |
T5 |
1596 |
2 |
0 |
0 |
T6 |
4922 |
13 |
0 |
0 |
T7 |
13291 |
35 |
0 |
0 |
T18 |
3121 |
48 |
0 |
0 |
T19 |
5218 |
3 |
0 |
0 |
T20 |
1961 |
16 |
0 |
0 |
T21 |
1746 |
9 |
0 |
0 |
T22 |
8456 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590773699 |
0 |
2415 |
T1 |
104860 |
104788 |
0 |
3 |
T4 |
58150 |
57921 |
0 |
3 |
T5 |
1596 |
1510 |
0 |
3 |
T6 |
4922 |
4736 |
0 |
3 |
T7 |
13291 |
13062 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
5218 |
5089 |
0 |
3 |
T20 |
1961 |
1789 |
0 |
3 |
T21 |
1746 |
1659 |
0 |
3 |
T22 |
8456 |
8326 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
36293 |
0 |
0 |
T1 |
104860 |
1 |
0 |
0 |
T4 |
58150 |
1 |
0 |
0 |
T5 |
1596 |
1 |
0 |
0 |
T6 |
4922 |
13 |
0 |
0 |
T7 |
13291 |
47 |
0 |
0 |
T18 |
3121 |
43 |
0 |
0 |
T19 |
5218 |
3 |
0 |
0 |
T20 |
1961 |
14 |
0 |
0 |
T21 |
1746 |
9 |
0 |
0 |
T22 |
8456 |
21 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590773699 |
0 |
2415 |
T1 |
104860 |
104788 |
0 |
3 |
T4 |
58150 |
57921 |
0 |
3 |
T5 |
1596 |
1510 |
0 |
3 |
T6 |
4922 |
4736 |
0 |
3 |
T7 |
13291 |
13062 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
5218 |
5089 |
0 |
3 |
T20 |
1961 |
1789 |
0 |
3 |
T21 |
1746 |
1659 |
0 |
3 |
T22 |
8456 |
8326 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
36202 |
0 |
0 |
T1 |
104860 |
1 |
0 |
0 |
T4 |
58150 |
1 |
0 |
0 |
T5 |
1596 |
1 |
0 |
0 |
T6 |
4922 |
5 |
0 |
0 |
T7 |
13291 |
31 |
0 |
0 |
T18 |
3121 |
50 |
0 |
0 |
T19 |
5218 |
3 |
0 |
0 |
T20 |
1961 |
5 |
0 |
0 |
T21 |
1746 |
7 |
0 |
0 |
T22 |
8456 |
29 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590773699 |
0 |
2415 |
T1 |
104860 |
104788 |
0 |
3 |
T4 |
58150 |
57921 |
0 |
3 |
T5 |
1596 |
1510 |
0 |
3 |
T6 |
4922 |
4736 |
0 |
3 |
T7 |
13291 |
13062 |
0 |
3 |
T18 |
3121 |
2964 |
0 |
3 |
T19 |
5218 |
5089 |
0 |
3 |
T20 |
1961 |
1789 |
0 |
3 |
T21 |
1746 |
1659 |
0 |
3 |
T22 |
8456 |
8326 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
36790 |
0 |
0 |
T1 |
104860 |
1 |
0 |
0 |
T4 |
58150 |
1 |
0 |
0 |
T5 |
1596 |
6 |
0 |
0 |
T6 |
4922 |
9 |
0 |
0 |
T7 |
13291 |
47 |
0 |
0 |
T18 |
3121 |
52 |
0 |
0 |
T19 |
5218 |
3 |
0 |
0 |
T20 |
1961 |
8 |
0 |
0 |
T21 |
1746 |
7 |
0 |
0 |
T22 |
8456 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595751743 |
590781133 |
0 |
0 |
T1 |
104860 |
104791 |
0 |
0 |
T4 |
58150 |
57924 |
0 |
0 |
T5 |
1596 |
1513 |
0 |
0 |
T6 |
4922 |
4739 |
0 |
0 |
T7 |
13291 |
13065 |
0 |
0 |
T18 |
3121 |
2967 |
0 |
0 |
T19 |
5218 |
5092 |
0 |
0 |
T20 |
1961 |
1792 |
0 |
0 |
T21 |
1746 |
1662 |
0 |
0 |
T22 |
8456 |
8329 |
0 |
0 |