Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T24,T2,T32

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	174108063	171236732	0	0
AllClkBypReqTrue_A	174108063	156636	0	0
IoClkBypReqFalse_A	174108063	171143047	0	2415
IoClkBypReqTrue_A	174108063	245413	0	0
LcClkBypAckFalse_A	174108063	171249212	0	0
LcClkBypAckTrue_A	174108063	144156	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	171236732	0	0
T1	8388	8382	0	0
T4	18275	18220	0	0
T5	1549	1412	0	0
T6	1181	1136	0	0
T7	3189	3134	0	0
T18	3121	2966	0	0
T19	1200	1171	0	0
T20	1882	1719	0	0
T21	1676	1491	0	0
T22	1690	1664	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	156636	0	0
T1	8388	0	0	0
T2	0	590	0	0
T4	18275	0	0	0
T5	1549	55	0	0
T6	1181	0	0	0
T7	3189	0	0	0
T11	0	984	0	0
T12	0	393	0	0
T13	0	456	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	104	0	0
T22	1690	0	0	0
T23	0	57	0	0
T30	0	85	0	0
T31	0	75	0	0
T100	0	118	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	171143047	0	2415
T1	8388	8380	0	3
T4	18275	18218	0	3
T5	1549	1316	0	3
T6	1181	1134	0	3
T7	3189	3132	0	3
T18	3121	2964	0	3
T19	1200	1169	0	3
T20	1882	1717	0	3
T21	1676	1474	0	3
T22	1690	1662	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	245413	0	0
T1	8388	0	0	0
T2	0	795	0	0
T4	18275	0	0	0
T5	1549	149	0	0
T6	1181	0	0	0
T7	3189	0	0	0
T11	0	1387	0	0
T12	0	546	0	0
T13	0	472	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	119	0	0
T22	1690	0	0	0
T23	0	80	0	0
T30	0	55	0	0
T31	0	356	0	0
T100	0	236	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	171249212	0	0
T1	8388	8382	0	0
T4	18275	18220	0	0
T5	1549	1429	0	0
T6	1181	1136	0	0
T7	3189	3134	0	0
T18	3121	2966	0	0
T19	1200	1171	0	0
T20	1882	1719	0	0
T21	1676	1518	0	0
T22	1690	1664	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	144156	0	0
T1	8388	0	0	0
T2	0	576	0	0
T4	18275	0	0	0
T5	1549	38	0	0
T6	1181	0	0	0
T7	3189	0	0	0
T11	0	855	0	0
T12	0	270	0	0
T13	0	277	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	77	0	0
T22	1690	0	0	0
T23	0	44	0	0
T30	0	21	0	0
T31	0	300	0	0
T100	0	134	0	0