Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16693	0	0
TransStop_A	2147483647	8765	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16693	0	0
T1	419444	0	0	0
T2	0	70	0	0
T4	232604	0	0	0
T6	19692	7	0	0
T7	53164	35	0	0
T11	0	108	0	0
T12	0	83	0	0
T13	0	177	0	0
T18	12488	31	0	0
T19	20876	0	0	0
T20	7848	0	0	0
T21	6988	0	0	0
T22	33828	34	0	0
T23	15728	0	0	0
T28	0	36	0	0
T101	0	33	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8765	0	0
T1	419444	0	0	0
T2	0	38	0	0
T4	232604	0	0	0
T6	14769	6	0	0
T7	53164	10	0	0
T11	0	69	0	0
T12	0	35	0	0
T13	0	82	0	0
T18	12488	18	0	0
T19	20876	0	0	0
T20	7848	0	0	0
T21	6988	0	0	0
T22	33828	23	0	0
T23	15728	0	0	0
T24	41289	0	0	0
T28	0	24	0	0
T57	0	3	0	0
T101	0	16	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	595752187	4159	0	0
TransStop_A	595752187	2189	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	4159	0	0
T1	104861	0	0	0
T2	0	18	0	0
T4	58151	0	0	0
T6	4923	1	0	0
T7	13291	9	0	0
T11	0	28	0	0
T12	0	18	0	0
T13	0	53	0	0
T18	3122	9	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	8	0	0
T23	3932	0	0	0
T28	0	11	0	0
T101	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	2189	0	0
T1	104861	0	0	0
T2	0	7	0	0
T4	58151	0	0	0
T7	13291	1	0	0
T11	0	18	0	0
T12	0	11	0	0
T13	0	24	0	0
T18	3122	5	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	5	0	0
T23	3932	0	0	0
T24	41289	0	0	0
T28	0	7	0	0
T57	0	3	0	0
T101	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	595752187	4230	0	0
TransStop_A	595752187	2169	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	4230	0	0
T1	104861	0	0	0
T2	0	24	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	11	0	0
T11	0	27	0	0
T12	0	25	0	0
T13	0	42	0	0
T18	3122	5	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	7	0	0
T23	3932	0	0	0
T28	0	7	0	0
T101	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	2169	0	0
T1	104861	0	0	0
T2	0	13	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	3	0	0
T11	0	17	0	0
T12	0	8	0	0
T13	0	21	0	0
T18	3122	4	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	5	0	0
T23	3932	0	0	0
T28	0	6	0	0
T101	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	595752187	4156	0	0
TransStop_A	595752187	2238	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	4156	0	0
T1	104861	0	0	0
T2	0	16	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	10	0	0
T11	0	28	0	0
T12	0	18	0	0
T13	0	37	0	0
T18	3122	10	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	11	0	0
T23	3932	0	0	0
T28	0	8	0	0
T101	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	2238	0	0
T1	104861	0	0	0
T2	0	10	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	3	0	0
T11	0	18	0	0
T12	0	6	0	0
T13	0	18	0	0
T18	3122	5	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	8	0	0
T23	3932	0	0	0
T28	0	5	0	0
T101	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	595752187	4148	0	0
TransStop_A	595752187	2169	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	4148	0	0
T1	104861	0	0	0
T2	0	12	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	5	0	0
T11	0	25	0	0
T12	0	22	0	0
T13	0	45	0	0
T18	3122	7	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	8	0	0
T23	3932	0	0	0
T28	0	10	0	0
T101	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595752187	2169	0	0
T1	104861	0	0	0
T2	0	8	0	0
T4	58151	0	0	0
T6	4923	2	0	0
T7	13291	3	0	0
T11	0	16	0	0
T12	0	10	0	0
T13	0	19	0	0
T18	3122	4	0	0
T19	5219	0	0	0
T20	1962	0	0	0
T21	1747	0	0	0
T22	8457	5	0	0
T23	3932	0	0	0
T28	0	6	0	0
T101	0	5	0	0