SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 348216126 | 342791644 | 0 | 0 |
gen_flops.OutputDelay_A | 348216126 | 342776362 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
T21 | 2 | 2 | 0 | 0 |
T22 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348216126 | 342791644 | 0 | 0 |
T1 | 16776 | 16766 | 0 | 0 |
T4 | 36550 | 36442 | 0 | 0 |
T5 | 3098 | 2936 | 0 | 0 |
T6 | 2362 | 2274 | 0 | 0 |
T7 | 6378 | 6270 | 0 | 0 |
T18 | 6242 | 5934 | 0 | 0 |
T19 | 2400 | 2344 | 0 | 0 |
T20 | 3764 | 3440 | 0 | 0 |
T21 | 3352 | 3192 | 0 | 0 |
T22 | 3380 | 3330 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348216126 | 342776362 | 0 | 4830 |
T1 | 16776 | 16760 | 0 | 6 |
T4 | 36550 | 36436 | 0 | 6 |
T5 | 3098 | 2930 | 0 | 6 |
T6 | 2362 | 2268 | 0 | 6 |
T7 | 6378 | 6264 | 0 | 6 |
T18 | 6242 | 5928 | 0 | 6 |
T19 | 2400 | 2338 | 0 | 6 |
T20 | 3764 | 3434 | 0 | 6 |
T21 | 3352 | 3186 | 0 | 6 |
T22 | 3380 | 3324 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 174108063 | 171395822 | 0 | 0 |
gen_flops.OutputDelay_A | 174108063 | 171388181 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174108063 | 171395822 | 0 | 0 |
T1 | 8388 | 8383 | 0 | 0 |
T4 | 18275 | 18221 | 0 | 0 |
T5 | 1549 | 1468 | 0 | 0 |
T6 | 1181 | 1137 | 0 | 0 |
T7 | 3189 | 3135 | 0 | 0 |
T18 | 3121 | 2967 | 0 | 0 |
T19 | 1200 | 1172 | 0 | 0 |
T20 | 1882 | 1720 | 0 | 0 |
T21 | 1676 | 1596 | 0 | 0 |
T22 | 1690 | 1665 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174108063 | 171388181 | 0 | 2415 |
T1 | 8388 | 8380 | 0 | 3 |
T4 | 18275 | 18218 | 0 | 3 |
T5 | 1549 | 1465 | 0 | 3 |
T6 | 1181 | 1134 | 0 | 3 |
T7 | 3189 | 3132 | 0 | 3 |
T18 | 3121 | 2964 | 0 | 3 |
T19 | 1200 | 1169 | 0 | 3 |
T20 | 1882 | 1717 | 0 | 3 |
T21 | 1676 | 1593 | 0 | 3 |
T22 | 1690 | 1662 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 174108063 | 171395822 | 0 | 0 |
gen_flops.OutputDelay_A | 174108063 | 171388181 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174108063 | 171395822 | 0 | 0 |
T1 | 8388 | 8383 | 0 | 0 |
T4 | 18275 | 18221 | 0 | 0 |
T5 | 1549 | 1468 | 0 | 0 |
T6 | 1181 | 1137 | 0 | 0 |
T7 | 3189 | 3135 | 0 | 0 |
T18 | 3121 | 2967 | 0 | 0 |
T19 | 1200 | 1172 | 0 | 0 |
T20 | 1882 | 1720 | 0 | 0 |
T21 | 1676 | 1596 | 0 | 0 |
T22 | 1690 | 1665 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174108063 | 171388181 | 0 | 2415 |
T1 | 8388 | 8380 | 0 | 3 |
T4 | 18275 | 18218 | 0 | 3 |
T5 | 1549 | 1465 | 0 | 3 |
T6 | 1181 | 1134 | 0 | 3 |
T7 | 3189 | 3132 | 0 | 3 |
T18 | 3121 | 2964 | 0 | 3 |
T19 | 1200 | 1169 | 0 | 3 |
T20 | 1882 | 1717 | 0 | 3 |
T21 | 1676 | 1593 | 0 | 3 |
T22 | 1690 | 1662 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |