Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	174108063	19991385	0	64

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	19991385	0	64
T1	8388	1814	0	1
T2	580446	23701	0	0
T3	0	8972	0	1
T4	18275	0	0	0
T11	0	30537	0	0
T12	0	8375	0	0
T13	0	154371	0	0
T14	0	377498	0	0
T15	0	6736	0	1
T16	0	94229	0	0
T17	0	12707	0	1
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T102	0	0	0	1
T103	0	0	0	1
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1