Line Coverage for Module :
clkmgr_extclk_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 34 | 1 | 1 | 100.00 |
ALWAYS | 49 | 1 | 1 | 100.00 |
ALWAYS | 66 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
49 |
1 |
1 |
66 |
1 |
1 |
Cond Coverage for Module :
clkmgr_extclk_sva_if
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (lc_clk_byp_req_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T5,T21,T23 |
1 | Covered | T5,T21,T23 |
LINE 49
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T21,T23 |
1 | 0 | Covered | T5,T23,T2 |
1 | 1 | Covered | T5,T21,T23 |
LINE 49
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T21,T23 |
1 | Covered | T5,T21,T23 |
LINE 49
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T5,T23,T2 |
1 | Covered | T5,T21,T23 |
LINE 66
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- -------------------2------------------- ------------3-----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T30,T11,T12 |
1 | 0 | 1 | Covered | T21,T2,T30 |
1 | 1 | 0 | Covered | T5,T2,T30 |
1 | 1 | 1 | Covered | T5,T21,T23 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T21,T23 |
1 | Covered | T5,T21,T23 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T5,T21,T23 |
1 | Covered | T5,T21,T23 |
LINE 66
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T5,T23,T2 |
1 | Covered | T5,T21,T23 |
Assert Coverage for Module :
clkmgr_extclk_sva_if
Assertion Details
AllClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
4786 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
20 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
1 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
24 |
0 |
0 |
T12 |
0 |
25 |
0 |
0 |
T13 |
0 |
8 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
6 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T30 |
0 |
9 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T100 |
0 |
4 |
0 |
0 |
AllClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
4786 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
20 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
1 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
24 |
0 |
0 |
T12 |
0 |
25 |
0 |
0 |
T13 |
0 |
8 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
6 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T30 |
0 |
9 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T100 |
0 |
4 |
0 |
0 |
HiSpeedSelFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
2854 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
11 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
1 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
15 |
0 |
0 |
T12 |
0 |
15 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
3 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T100 |
0 |
3 |
0 |
0 |
HiSpeedSelRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
2854 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
11 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
1 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
15 |
0 |
0 |
T12 |
0 |
15 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
3 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T100 |
0 |
3 |
0 |
0 |
IoClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
6015 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
19 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
3 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T12 |
0 |
20 |
0 |
0 |
T13 |
0 |
7 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
4 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
T100 |
0 |
8 |
0 |
0 |
IoClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174108063 |
6015 |
0 |
0 |
T1 |
8388 |
0 |
0 |
0 |
T2 |
0 |
19 |
0 |
0 |
T4 |
18275 |
0 |
0 |
0 |
T5 |
1549 |
3 |
0 |
0 |
T6 |
1181 |
0 |
0 |
0 |
T7 |
3189 |
0 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T12 |
0 |
20 |
0 |
0 |
T13 |
0 |
7 |
0 |
0 |
T18 |
3121 |
0 |
0 |
0 |
T19 |
1200 |
0 |
0 |
0 |
T20 |
1882 |
0 |
0 |
0 |
T21 |
1676 |
4 |
0 |
0 |
T22 |
1690 |
0 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
T100 |
0 |
8 |
0 |
0 |