Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	175034241	5838358	0	0
clk_enables_rd_A	175034241	63496	0	0
clk_hints_rd_A	175034241	54867	0	0
extclk_ctrl_rd_A	175034241	69993	0	0
extclk_ctrl_regwen_rd_A	175034241	53857	0	0
jitter_enable_rd_A	175034241	74764	0	0
jitter_regwen_rd_A	175034241	61124	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	5838358	0	0
T13	134597	38967	0	0
T14	296495	143257	0	0
T16	0	78463	0	0
T26	0	41553	0	0
T37	0	91771	0	0
T52	0	208217	0	0
T53	0	122014	0	0
T54	0	67945	0	0
T55	0	102481	0	0
T56	0	143045	0	0
T57	2000	0	0	0
T58	1300	0	0	0
T59	1416	0	0	0
T60	1294	0	0	0
T61	684	0	0	0
T62	2013	0	0	0
T63	1446	0	0	0
T64	1332	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	63496	0	0
T8	30938	0	0	0
T11	318195	29	0	0
T12	51991	0	0	0
T13	134597	1541	0	0
T26	0	1768	0	0
T34	12994	0	0	0
T39	1263	0	0	0
T53	0	4778	0	0
T54	0	1574	0	0
T56	0	5257	0	0
T100	1091	0	0	0
T101	2993	0	0	0
T108	24489	0	0	0
T128	0	6	0	0
T129	0	2	0	0
T130	0	3979	0	0
T131	0	11	0	0
T132	935	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	54867	0	0
T2	580446	6	0	0
T3	51862	0	0	0
T11	0	14	0	0
T13	0	1302	0	0
T25	52851	0	0	0
T26	0	1510	0	0
T27	888	0	0	0
T28	2230	0	0	0
T29	1662	0	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T53	0	3871	0	0
T54	0	1237	0	0
T56	0	4762	0	0
T128	0	1	0	0
T129	0	3	0	0
T130	0	3131	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	69993	0	0
T1	8388	0	0	0
T2	0	37	0	0
T4	18275	0	0	0
T5	1549	28	0	0
T6	1181	0	0	0
T7	3189	0	0	0
T11	0	140	0	0
T13	0	1347	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T25	0	77	0	0
T26	0	1714	0	0
T27	0	4	0	0
T31	0	52	0	0
T80	0	21	0	0
T133	0	16	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	53857	0	0
T8	30938	0	0	0
T11	318195	0	0	0
T12	51991	0	0	0
T13	0	1332	0	0
T25	52851	20	0	0
T26	0	1392	0	0
T33	33319	0	0	0
T34	12994	0	0	0
T39	1263	0	0	0
T53	0	3908	0	0
T54	0	1408	0	0
T56	0	4725	0	0
T99	0	33	0	0
T100	1091	0	0	0
T101	2993	0	0	0
T130	0	3426	0	0
T132	935	0	0	0
T134	0	7	0	0
T135	0	4810	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	74764	0	0
T2	580446	79	0	0
T3	51862	0	0	0
T11	0	646	0	0
T13	0	1889	0	0
T25	52851	0	0	0
T26	0	1751	0	0
T27	888	0	0	0
T28	2230	0	0	0
T29	1662	0	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T53	0	7349	0	0
T54	0	1593	0	0
T56	0	5603	0	0
T128	0	80	0	0
T129	0	97	0	0
T130	0	4075	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	61124	0	0
T13	134597	1421	0	0
T14	296495	0	0	0
T26	0	1648	0	0
T53	0	4595	0	0
T54	0	1416	0	0
T56	0	5285	0	0
T57	2000	0	0	0
T58	1300	0	0	0
T59	1416	0	0	0
T60	1294	0	0	0
T61	684	0	0	0
T62	2013	0	0	0
T63	1446	0	0	0
T64	1332	0	0	0
T130	0	3889	0	0
T135	0	5547	0	0
T136	0	1166	0	0
T137	0	1736	0	0
T138	0	1776	0	0