Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1750342410	1538124	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1750342410	327690	0	0
SrcBusyKnown_A	1750342410	1722122840	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1750342410	1538124	0	0
T1	83880	364	0	0
T2	5804460	8182	0	0
T3	0	1334	0	0
T4	182750	408	0	0
T8	0	1291	0	0
T11	0	5457	0	0
T12	0	2114	0	0
T18	31210	0	0	0
T19	12000	0	0	0
T20	18820	0	0	0
T21	16760	0	0	0
T22	16900	0	0	0
T23	12980	0	0	0
T24	198190	0	0	0
T25	0	2353	0	0
T33	0	1606	0	0
T34	0	678	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	662666	662270	0	0
T4	433602	432312	0	0
T5	10120	9634	0	0
T6	30930	29952	0	0
T7	83856	82568	0	0
T18	19608	18754	0	0
T19	32900	32184	0	0
T20	12190	11324	0	0
T21	11226	10756	0	0
T22	53384	52644	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1750342410	327690	0	0
T1	83880	140	0	0
T2	5804460	980	0	0
T3	0	380	0	0
T4	182750	120	0	0
T8	0	196	0	0
T11	0	1280	0	0
T12	0	820	0	0
T18	31210	0	0	0
T19	12000	0	0	0
T20	18820	0	0	0
T21	16760	0	0	0
T22	16900	0	0	0
T23	12980	0	0	0
T24	198190	0	0	0
T25	0	470	0	0
T33	0	392	0	0
T34	0	202	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1750342410	1722122840	0	0
T1	83880	83830	0	0
T4	182750	182210	0	0
T5	15490	14680	0	0
T6	11810	11370	0	0
T7	31890	31350	0	0
T18	31210	29670	0	0
T19	12000	11720	0	0
T20	18820	17200	0	0
T21	16760	15960	0	0
T22	16900	16650	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	98823	0	0
DstReqKnown_A	561368002	556487925	0	0
SrcAckBusyChk_A	175034241	29808	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	98823	0	0
T1	8388	35	0	0
T2	580446	584	0	0
T3	0	99	0	0
T4	18275	30	0	0
T8	0	58	0	0
T11	0	405	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	111	0	0
T33	0	81	0	0
T34	0	35	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561368002	556487925	0	0
T1	100662	100596	0	0
T4	73102	72885	0	0
T5	1532	1453	0	0
T6	4726	4550	0	0
T7	12759	12542	0	0
T18	2997	2849	0	0
T19	5010	4889	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	8118	7997	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	29808	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	14	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	32	0	0
T33	0	28	0	0
T34	0	14	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	138663	0	0
DstReqKnown_A	280290249	279078100	0	0
SrcAckBusyChk_A	175034241	29808	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	138663	0	0
T1	8388	35	0	0
T2	580446	839	0	0
T3	0	137	0	0
T4	18275	42	0	0
T8	0	93	0	0
T11	0	551	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	157	0	0
T33	0	111	0	0
T34	0	49	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280290249	279078100	0	0
T1	50319	50298	0	0
T4	36504	36442	0	0
T5	778	751	0	0
T6	2303	2275	0	0
T7	6333	6271	0	0
T18	1459	1425	0	0
T19	2479	2445	0	0
T20	874	860	0	0
T21	902	881	0	0
T22	4040	3999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	29808	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	14	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	32	0	0
T33	0	28	0	0
T34	0	14	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	215610	0	0
DstReqKnown_A	140144402	139538435	0	0
SrcAckBusyChk_A	175034241	29808	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	215610	0	0
T1	8388	42	0	0
T2	580446	1427	0	0
T3	0	195	0	0
T4	18275	60	0	0
T8	0	158	0	0
T11	0	848	0	0
T12	0	226	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	249	0	0
T33	0	170	0	0
T34	0	70	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140144402	139538435	0	0
T1	25159	25149	0	0
T4	18252	18221	0	0
T5	388	374	0	0
T6	1151	1137	0	0
T7	3166	3135	0	0
T18	729	712	0	0
T19	1239	1222	0	0
T20	437	430	0	0
T21	451	441	0	0
T22	2020	1999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	29808	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	14	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	32	0	0
T33	0	28	0	0
T34	0	14	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	96503	0	0
DstReqKnown_A	598512351	593352667	0	0
SrcAckBusyChk_A	175034241	29808	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	96503	0	0
T1	8388	35	0	0
T2	580446	476	0	0
T3	0	99	0	0
T4	18275	30	0	0
T8	0	57	0	0
T11	0	396	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	106	0	0
T33	0	79	0	0
T34	0	35	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598512351	593352667	0	0
T1	104860	104791	0	0
T4	58150	57924	0	0
T5	1596	1513	0	0
T6	4922	4739	0	0
T7	13291	13065	0	0
T18	3121	2967	0	0
T19	5218	5092	0	0
T20	1961	1792	0	0
T21	1746	1662	0	0
T22	8456	8329	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	29808	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	14	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	32	0	0
T33	0	28	0	0
T34	0	14	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	137338	0	0
DstReqKnown_A	287270380	284801940	0	0
SrcAckBusyChk_A	175034241	29255	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	137338	0	0
T1	8388	35	0	0
T2	580446	770	0	0
T3	0	135	0	0
T4	18275	42	0	0
T8	0	52	0	0
T11	0	538	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	130	0	0
T33	0	69	0	0
T34	0	31	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287270380	284801940	0	0
T1	50333	50301	0	0
T4	30793	30684	0	0
T5	766	726	0	0
T6	2363	2275	0	0
T7	6379	6271	0	0
T18	1498	1424	0	0
T19	2504	2444	0	0
T20	941	860	0	0
T21	838	798	0	0
T22	4058	3998	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	29255	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	7	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	22	0	0
T33	0	14	0	0
T34	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	121564	0	0
DstReqKnown_A	561368002	556487925	0	0
SrcAckBusyChk_A	175034241	36002	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	121564	0	0
T1	8388	35	0	0
T2	580446	582	0	0
T3	0	100	0	0
T4	18275	30	0	0
T8	0	119	0	0
T11	0	403	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	224	0	0
T33	0	164	0	0
T34	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561368002	556487925	0	0
T1	100662	100596	0	0
T4	73102	72885	0	0
T5	1532	1453	0	0
T6	4726	4550	0	0
T7	12759	12542	0	0
T18	2997	2849	0	0
T19	5010	4889	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	8118	7997	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	36002	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	28	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	64	0	0
T33	0	56	0	0
T34	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	171410	0	0
DstReqKnown_A	280290249	279078100	0	0
SrcAckBusyChk_A	175034241	35871	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	171410	0	0
T1	8388	35	0	0
T2	580446	822	0	0
T3	0	135	0	0
T4	18275	42	0	0
T8	0	179	0	0
T11	0	541	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	320	0	0
T33	0	219	0	0
T34	0	95	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280290249	279078100	0	0
T1	50319	50298	0	0
T4	36504	36442	0	0
T5	778	751	0	0
T6	2303	2275	0	0
T7	6333	6271	0	0
T18	1459	1425	0	0
T19	2479	2445	0	0
T20	874	860	0	0
T21	902	881	0	0
T22	4040	3999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	35871	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	28	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	64	0	0
T33	0	56	0	0
T34	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	268536	0	0
DstReqKnown_A	140144402	139538435	0	0
SrcAckBusyChk_A	175034241	35924	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	268536	0	0
T1	8388	42	0	0
T2	580446	1429	0	0
T3	0	197	0	0
T4	18275	60	0	0
T8	0	304	0	0
T11	0	844	0	0
T12	0	232	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	515	0	0
T33	0	343	0	0
T34	0	134	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140144402	139538435	0	0
T1	25159	25149	0	0
T4	18252	18221	0	0
T5	388	374	0	0
T6	1151	1137	0	0
T7	3166	3135	0	0
T18	729	712	0	0
T19	1239	1222	0	0
T20	437	430	0	0
T21	451	441	0	0
T22	2020	1999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	35924	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	28	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	64	0	0
T33	0	56	0	0
T34	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	118177	0	0
DstReqKnown_A	598512351	593352667	0	0
SrcAckBusyChk_A	175034241	35866	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	118177	0	0
T1	8388	35	0	0
T2	580446	473	0	0
T3	0	100	0	0
T4	18275	30	0	0
T8	0	115	0	0
T11	0	392	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	221	0	0
T33	0	160	0	0
T34	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598512351	593352667	0	0
T1	104860	104791	0	0
T4	58150	57924	0	0
T5	1596	1513	0	0
T6	4922	4739	0	0
T7	13291	13065	0	0
T18	3121	2967	0	0
T19	5218	5092	0	0
T20	1961	1792	0	0
T21	1746	1662	0	0
T22	8456	8329	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	35866	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	28	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	64	0	0
T33	0	56	0	0
T34	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T25,T33,T34
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175034241	171500	0	0
DstReqKnown_A	287270380	284801940	0	0
SrcAckBusyChk_A	175034241	35540	0	0
SrcBusyKnown_A	175034241	172212284	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	171500	0	0
T1	8388	35	0	0
T2	580446	780	0	0
T3	0	137	0	0
T4	18275	42	0	0
T8	0	156	0	0
T11	0	539	0	0
T12	0	207	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	320	0	0
T33	0	210	0	0
T34	0	95	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287270380	284801940	0	0
T1	50333	50301	0	0
T4	30793	30684	0	0
T5	766	726	0	0
T6	2363	2275	0	0
T7	6379	6271	0	0
T18	1498	1424	0	0
T19	2504	2444	0	0
T20	941	860	0	0
T21	838	798	0	0
T22	4058	3998	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	35540	0	0
T1	8388	14	0	0
T2	580446	98	0	0
T3	0	38	0	0
T4	18275	12	0	0
T8	0	21	0	0
T11	0	128	0	0
T12	0	82	0	0
T18	3121	0	0	0
T19	1200	0	0	0
T20	1882	0	0	0
T21	1676	0	0	0
T22	1690	0	0	0
T23	1298	0	0	0
T24	19819	0	0	0
T25	0	64	0	0
T33	0	42	0	0
T34	0	27	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175034241	172212284	0	0
T1	8388	8383	0	0
T4	18275	18221	0	0
T5	1549	1468	0	0
T6	1181	1137	0	0
T7	3189	3135	0	0
T18	3121	2967	0	0
T19	1200	1172	0	0
T20	1882	1720	0	0
T21	1676	1596	0	0
T22	1690	1665	0	0