Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T21,T2
1	1	Covered	T5,T21,T23

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	558718359	5379	0	0
g_div2.Div2Whole_A	558718359	6097	0	0
g_div4.Div4Stepped_A	279009990	5313	0	0
g_div4.Div4Whole_A	279009990	5918	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	5379	0	0
T1	100663	0	0	0
T2	0	15	0	0
T4	73103	0	0	0
T5	1533	1	0	0
T6	4726	0	0	0
T7	12760	0	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	0	7	0	0
T18	2997	0	0	0
T19	5010	0	0	0
T20	1883	0	0	0
T21	1677	5	0	0
T22	8118	0	0	0
T23	0	2	0	0
T30	0	1	0	0
T31	0	7	0	0
T100	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	6097	0	0
T1	100663	0	0	0
T2	0	23	0	0
T4	73103	0	0	0
T5	1533	1	0	0
T6	4726	0	0	0
T7	12760	0	0	0
T11	0	27	0	0
T12	0	26	0	0
T13	0	8	0	0
T18	2997	0	0	0
T19	5010	0	0	0
T20	1883	0	0	0
T21	1677	5	0	0
T22	8118	0	0	0
T23	0	2	0	0
T30	0	8	0	0
T31	0	7	0	0
T100	0	6	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	5313	0	0
T1	50319	0	0	0
T2	0	15	0	0
T4	36505	0	0	0
T5	778	1	0	0
T6	2303	0	0	0
T7	6333	0	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	0	7	0	0
T18	1459	0	0	0
T19	2479	0	0	0
T20	875	0	0	0
T21	902	5	0	0
T22	4040	0	0	0
T23	0	2	0	0
T30	0	1	0	0
T31	0	7	0	0
T100	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	5918	0	0
T1	50319	0	0	0
T2	0	20	0	0
T4	36505	0	0	0
T5	778	1	0	0
T6	2303	0	0	0
T7	6333	0	0	0
T11	0	27	0	0
T12	0	25	0	0
T13	0	8	0	0
T18	1459	0	0	0
T19	2479	0	0	0
T20	875	0	0	0
T21	902	4	0	0
T22	4040	0	0	0
T23	0	2	0	0
T30	0	7	0	0
T31	0	7	0	0
T100	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T21,T2
1	1	Covered	T5,T21,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	558718359	5379	0	0
g_div2.Div2Whole_A	558718359	6097	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	5379	0	0
T1	100663	0	0	0
T2	0	15	0	0
T4	73103	0	0	0
T5	1533	1	0	0
T6	4726	0	0	0
T7	12760	0	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	0	7	0	0
T18	2997	0	0	0
T19	5010	0	0	0
T20	1883	0	0	0
T21	1677	5	0	0
T22	8118	0	0	0
T23	0	2	0	0
T30	0	1	0	0
T31	0	7	0	0
T100	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558718359	6097	0	0
T1	100663	0	0	0
T2	0	23	0	0
T4	73103	0	0	0
T5	1533	1	0	0
T6	4726	0	0	0
T7	12760	0	0	0
T11	0	27	0	0
T12	0	26	0	0
T13	0	8	0	0
T18	2997	0	0	0
T19	5010	0	0	0
T20	1883	0	0	0
T21	1677	5	0	0
T22	8118	0	0	0
T23	0	2	0	0
T30	0	8	0	0
T31	0	7	0	0
T100	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T21,T2
1	1	Covered	T5,T21,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	279009990	5313	0	0
g_div4.Div4Whole_A	279009990	5918	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	5313	0	0
T1	50319	0	0	0
T2	0	15	0	0
T4	36505	0	0	0
T5	778	1	0	0
T6	2303	0	0	0
T7	6333	0	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	0	7	0	0
T18	1459	0	0	0
T19	2479	0	0	0
T20	875	0	0	0
T21	902	5	0	0
T22	4040	0	0	0
T23	0	2	0	0
T30	0	1	0	0
T31	0	7	0	0
T100	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009990	5918	0	0
T1	50319	0	0	0
T2	0	20	0	0
T4	36505	0	0	0
T5	778	1	0	0
T6	2303	0	0	0
T7	6333	0	0	0
T11	0	27	0	0
T12	0	25	0	0
T13	0	8	0	0
T18	1459	0	0	0
T19	2479	0	0	0
T20	875	0	0	0
T21	902	4	0	0
T22	4040	0	0	0
T23	0	2	0	0
T30	0	7	0	0
T31	0	7	0	0
T100	0	6	0	0