Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	522324189	471	0	0
StatusRise_A	522324189	471	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522324189	471	0	0
T3	155586	0	0	0
T11	954585	0	0	0
T25	158553	0	0	0
T29	4986	10	0	0
T30	6678	0	0	0
T31	6567	0	0	0
T32	91068	0	0	0
T33	99957	0	0	0
T39	0	8	0	0
T40	0	13	0	0
T100	3273	0	0	0
T132	2805	0	0	0
T139	0	8	0	0
T140	0	10	0	0
T141	0	3	0	0
T142	0	17	0	0
T143	0	3	0	0
T144	0	14	0	0
T145	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522324189	471	0	0
T3	155586	0	0	0
T11	954585	0	0	0
T25	158553	0	0	0
T29	4986	10	0	0
T30	6678	0	0	0
T31	6567	0	0	0
T32	91068	0	0	0
T33	99957	0	0	0
T39	0	8	0	0
T40	0	13	0	0
T100	3273	0	0	0
T132	2805	0	0	0
T139	0	8	0	0
T140	0	10	0	0
T141	0	3	0	0
T142	0	17	0	0
T143	0	3	0	0
T144	0	14	0	0
T145	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174108063	164	0	0
StatusRise_A	174108063	164	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	164	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	3	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	164	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	3	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174108063	154	0	0
StatusRise_A	174108063	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	154	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	3	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	154	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	3	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174108063	153	0	0
StatusRise_A	174108063	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	153	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	4	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	4	0	0
T145	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174108063	153	0	0
T3	51862	0	0	0
T11	318195	0	0	0
T25	52851	0	0	0
T29	1662	4	0	0
T30	2226	0	0	0
T31	2189	0	0	0
T32	30356	0	0	0
T33	33319	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T100	1091	0	0	0
T132	935	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	4	0	0
T145	0	3	0	0