Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	53226	0	0
CgEnOn_A	2147483647	43414	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53226	0	0
T1	281000	3	0	0
T2	0	18	0	0
T3	486912	0	0	0
T4	186008	3	0	0
T5	2698	3	0	0
T6	13102	4	0	0
T7	35549	12	0	0
T11	1681014	0	0	0
T18	8306	12	0	0
T19	13946	3	0	0
T20	5154	31	0	0
T21	4775	3	0	0
T22	22634	11	0	0
T23	3932	0	0	0
T25	178895	0	0	0
T29	3050	18	0	0
T30	4836	0	0	0
T31	10080	0	0	0
T32	55200	0	0	0
T33	154626	0	0	0
T37	0	5	0	0
T39	0	18	0	0
T40	0	25	0	0
T100	50805	0	0	0
T132	8033	0	0	0
T139	0	10	0	0
T140	0	20	0	0
T141	0	5	0	0
T142	0	25	0	0
T143	0	5	0	0
T146	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43414	0	0
T2	834346	64	0	0
T3	486912	0	0	0
T4	186008	0	0	0
T6	4922	1	0	0
T7	13291	9	0	0
T11	1681014	46	0	0
T12	0	62	0	0
T13	0	229	0	0
T20	5154	28	0	0
T21	4775	0	0	0
T22	22634	0	0	0
T23	10619	0	0	0
T24	63220	0	0	0
T25	178895	0	0	0
T27	6148	0	0	0
T28	7785	0	0	0
T29	5446	27	0	0
T30	4836	0	0	0
T31	10080	0	0	0
T32	55200	0	0	0
T33	154626	0	0	0
T37	0	4	0	0
T39	0	27	0	0
T40	0	25	0	0
T58	0	3	0	0
T59	0	9	0	0
T100	50805	0	0	0
T132	8033	22	0	0
T139	0	10	0	0
T140	0	20	0	0
T141	0	5	0	0
T142	0	25	0	0
T143	0	5	0	0
T144	0	5	0	0
T146	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	279009589	164	0	0
CgEnOn_A	279009589	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009589	164	0	0
T3	108182	0	0	0
T11	373910	0	0	0
T25	30142	0	0	0
T29	654	3	0	0
T30	1082	0	0	0
T31	2352	0	0	0
T32	10429	0	0	0
T33	24219	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	11935	0	0	0
T132	1777	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009589	164	0	0
T3	108182	0	0	0
T11	373910	0	0	0
T25	30142	0	0	0
T29	654	3	0	0
T30	1082	0	0	0
T31	2352	0	0	0
T32	10429	0	0	0
T33	24219	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	11935	0	0	0
T132	1777	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139504068	164	0	0
CgEnOn_A	139504068	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139504068	164	0	0
CgEnOn_A	139504068	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139504068	164	0	0
CgEnOn_A	139504068	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	164	0	0
T3	54091	0	0	0
T11	186953	0	0	0
T25	15071	0	0	0
T29	327	3	0	0
T30	539	0	0	0
T31	1175	0	0	0
T32	5210	0	0	0
T33	12110	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	5967	0	0	0
T132	888	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558717927	164	0	0
CgEnOn_A	558717927	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558717927	164	0	0
T3	216457	0	0	0
T11	746245	0	0	0
T25	103540	0	0	0
T29	1415	3	0	0
T30	2137	0	0	0
T31	4203	0	0	0
T32	29141	0	0	0
T33	94077	0	0	0
T37	0	1	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	20969	0	0	0
T132	3592	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558717927	158	0	0
T3	216457	0	0	0
T11	746245	0	0	0
T25	103540	0	0	0
T29	1415	3	0	0
T30	2137	0	0	0
T31	4203	0	0	0
T32	29141	0	0	0
T33	94077	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T100	20969	0	0	0
T132	3592	0	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	5	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	166	0	0
CgEnOn_A	595751743	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	166	0	0
T3	225483	0	0	0
T11	825363	0	0	0
T25	107858	0	0	0
T29	1572	3	0	0
T30	2226	0	0	0
T31	4378	0	0	0
T32	30356	0	0	0
T33	98001	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T56	0	1	0	0
T100	21843	0	0	0
T132	3742	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	164	0	0
T3	225483	0	0	0
T11	825363	0	0	0
T25	107858	0	0	0
T29	1572	3	0	0
T30	2226	0	0	0
T31	4378	0	0	0
T32	30356	0	0	0
T33	98001	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T100	21843	0	0	0
T132	3742	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	166	0	0
CgEnOn_A	595751743	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	166	0	0
T3	225483	0	0	0
T11	825363	0	0	0
T25	107858	0	0	0
T29	1572	3	0	0
T30	2226	0	0	0
T31	4378	0	0	0
T32	30356	0	0	0
T33	98001	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T56	0	1	0	0
T100	21843	0	0	0
T132	3742	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	164	0	0
T3	225483	0	0	0
T11	825363	0	0	0
T25	107858	0	0	0
T29	1572	3	0	0
T30	2226	0	0	0
T31	4378	0	0	0
T32	30356	0	0	0
T33	98001	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T100	21843	0	0	0
T132	3742	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	285945322	157	0	0
CgEnOn_A	285945322	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945322	157	0	0
T3	108233	0	0	0
T11	390420	0	0	0
T25	51772	0	0	0
T29	747	4	0	0
T30	1069	0	0	0
T31	2101	0	0	0
T32	14571	0	0	0
T33	47041	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T100	10484	0	0	0
T132	1796	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	4	0	0
T145	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945322	154	0	0
T3	108233	0	0	0
T11	390420	0	0	0
T25	51772	0	0	0
T29	747	4	0	0
T30	1069	0	0	0
T31	2101	0	0	0
T32	14571	0	0	0
T33	47041	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T100	10484	0	0	0
T132	1796	0	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	6	0	0
T143	0	1	0	0
T144	0	4	0	0
T145	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139504068	8581	0	0
CgEnOn_A	139504068	6137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	8581	0	0
T1	25159	1	0	0
T4	18252	1	0	0
T5	388	1	0	0
T6	1151	1	0	0
T7	3166	1	0	0
T18	729	1	0	0
T19	1239	1	0	0
T20	437	11	0	0
T21	451	1	0	0
T22	2020	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139504068	6137	0	0
T2	119191	15	0	0
T4	18252	0	0	0
T11	0	6	0	0
T12	0	19	0	0
T13	0	80	0	0
T20	437	10	0	0
T21	451	0	0	0
T22	2020	0	0	0
T23	971	0	0	0
T24	7863	0	0	0
T27	865	0	0	0
T28	1109	0	0	0
T29	327	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	3	0	0
T132	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	279009589	8643	0	0
CgEnOn_A	279009589	6199	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009589	8643	0	0
T1	50319	1	0	0
T4	36504	1	0	0
T5	778	1	0	0
T6	2303	1	0	0
T7	6333	1	0	0
T18	1459	1	0	0
T19	2479	1	0	0
T20	874	10	0	0
T21	902	1	0	0
T22	4040	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279009589	6199	0	0
T2	238386	16	0	0
T4	36504	0	0	0
T11	0	6	0	0
T12	0	22	0	0
T13	0	74	0	0
T20	874	9	0	0
T21	902	0	0	0
T22	4040	0	0	0
T23	1942	0	0	0
T24	15722	0	0	0
T27	1730	0	0	0
T28	2217	0	0	0
T29	654	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	3	0	0
T132	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558717927	8662	0	0
CgEnOn_A	558717927	6212	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558717927	8662	0	0
T1	100662	1	0	0
T4	73102	1	0	0
T5	1532	1	0	0
T6	4726	1	0	0
T7	12759	1	0	0
T18	2997	1	0	0
T19	5010	1	0	0
T20	1882	10	0	0
T21	1676	1	0	0
T22	8118	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558717927	6212	0	0
T2	476769	15	0	0
T4	73102	0	0	0
T11	0	6	0	0
T12	0	21	0	0
T13	0	75	0	0
T20	1882	9	0	0
T21	1676	0	0	0
T22	8118	0	0	0
T23	3774	0	0	0
T24	39635	0	0	0
T27	3553	0	0	0
T28	4459	0	0	0
T29	1415	3	0	0
T39	0	3	0	0
T58	0	1	0	0
T59	0	3	0	0
T132	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	285945322	8674	0	0
CgEnOn_A	285945322	6221	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945322	8674	0	0
T1	50333	1	0	0
T4	30793	1	0	0
T5	766	1	0	0
T6	2363	1	0	0
T7	6379	1	0	0
T18	1498	1	0	0
T19	2504	1	0	0
T20	941	10	0	0
T21	838	1	0	0
T22	4058	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285945322	6221	0	0
T2	278717	17	0	0
T4	30793	0	0	0
T11	0	6	0	0
T12	0	21	0	0
T13	0	72	0	0
T20	941	9	0	0
T21	838	0	0	0
T22	4058	0	0	0
T23	1887	0	0	0
T24	19819	0	0	0
T27	1777	0	0	0
T28	2230	0	0	0
T29	747	4	0	0
T39	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T132	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Covered	T6,T7,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	4325	0	0
CgEnOn_A	595751743	4323	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4325	0	0
T1	104860	0	0	0
T2	0	18	0	0
T4	58150	0	0	0
T6	4922	1	0	0
T7	13291	9	0	0
T11	0	28	0	0
T18	3121	9	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	8	0	0
T23	3932	0	0	0
T28	0	11	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4323	0	0
T1	104860	0	0	0
T2	0	18	0	0
T4	58150	0	0	0
T6	4922	1	0	0
T7	13291	9	0	0
T11	0	28	0	0
T18	3121	9	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	8	0	0
T23	3932	0	0	0
T28	0	11	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Covered	T6,T7,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	4396	0	0
CgEnOn_A	595751743	4394	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4396	0	0
T1	104860	0	0	0
T2	0	24	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	11	0	0
T11	0	27	0	0
T18	3121	5	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	7	0	0
T23	3932	0	0	0
T28	0	7	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4394	0	0
T1	104860	0	0	0
T2	0	24	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	11	0	0
T11	0	27	0	0
T18	3121	5	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	7	0	0
T23	3932	0	0	0
T28	0	7	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Covered	T6,T7,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	4322	0	0
CgEnOn_A	595751743	4320	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4322	0	0
T1	104860	0	0	0
T2	0	16	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	10	0	0
T11	0	28	0	0
T18	3121	10	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	11	0	0
T23	3932	0	0	0
T28	0	8	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4320	0	0
T1	104860	0	0	0
T2	0	16	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	10	0	0
T11	0	28	0	0
T18	3121	10	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	11	0	0
T23	3932	0	0	0
T28	0	8	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T29
1	0	Covered	T6,T7,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595751743	4314	0	0
CgEnOn_A	595751743	4312	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4314	0	0
T1	104860	0	0	0
T2	0	12	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	5	0	0
T11	0	25	0	0
T18	3121	7	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	8	0	0
T23	3932	0	0	0
T28	0	10	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595751743	4312	0	0
T1	104860	0	0	0
T2	0	12	0	0
T4	58150	0	0	0
T6	4922	2	0	0
T7	13291	5	0	0
T11	0	25	0	0
T18	3121	7	0	0
T19	5218	0	0	0
T20	1961	0	0	0
T21	1746	0	0	0
T22	8456	8	0	0
T23	3932	0	0	0
T28	0	10	0	0
T29	0	3	0	0
T39	0	3	0	0
T101	0	10	0	0