Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	614475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3629559

1

T6

6

T7

20

T8

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1046481	1			T7	36		T8	27		T23	4
values[0x0]	1468795	1			T6	9		T7	11		T8	19
values[0x1]	1728758	1			T6	12		T7	16		T8	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3909495

1

T6

8

T7

25

T8

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15557	1			T1	675		T5	2		T4	2
valid_sources[0x01]	14887	1			T8	1		T1	34		T4	10
valid_sources[0x02]	16516	1			T1	135		T5	1		T4	3
valid_sources[0x03]	16298	1			T8	2		T1	254		T5	3
valid_sources[0x04]	16521	1			T1	558		T4	7		T26	2
valid_sources[0x05]	17518	1			T1	533		T26	3		T10	5
valid_sources[0x06]	15902	1			T8	1		T1	696		T4	4
valid_sources[0x07]	16726	1			T8	1		T1	155		T26	4
valid_sources[0x08]	16963	1			T1	625		T26	2		T10	160
valid_sources[0x09]	16149	1			T1	166		T21	2		T4	4
valid_sources[0x0a]	16069	1			T1	158		T5	8		T26	8
valid_sources[0x0b]	18733	1			T1	1		T22	3		T4	4
valid_sources[0x0c]	16379	1			T1	3		T5	1		T20	1
valid_sources[0x0d]	15877	1			T8	1		T1	281		T26	2
valid_sources[0x0e]	17218	1			T1	759		T10	1		T27	2
valid_sources[0x0f]	16987	1			T1	69		T5	3		T4	3
valid_sources[0x10]	15850	1			T1	216		T4	2		T26	1
valid_sources[0x11]	17862	1			T6	1		T1	367		T5	3
valid_sources[0x12]	16250	1			T1	507		T5	2		T4	9
valid_sources[0x13]	16893	1			T1	447		T20	1		T26	3
valid_sources[0x14]	15308	1			T1	124		T5	2		T4	2
valid_sources[0x15]	17070	1			T6	1		T1	157		T26	1
valid_sources[0x16]	15889	1			T5	4		T4	8		T26	5
valid_sources[0x17]	16733	1			T1	163		T5	18		T4	12
valid_sources[0x18]	15378	1			T8	1		T1	506		T5	9
valid_sources[0x19]	17568	1			T8	1		T1	267		T4	1
valid_sources[0x1a]	16838	1			T1	623		T4	14		T97	1
valid_sources[0x1b]	16566	1			T8	1		T23	1		T1	35
valid_sources[0x1c]	15499	1			T6	2		T1	689		T5	1
valid_sources[0x1d]	17390	1			T1	335		T5	11		T10	45
valid_sources[0x1e]	15965	1			T1	325		T4	1		T26	2
valid_sources[0x1f]	16880	1			T1	89		T4	8		T97	2
valid_sources[0x20]	15448	1			T1	246		T5	7		T4	2
valid_sources[0x21]	17545	1			T1	366		T10	240		T27	7
valid_sources[0x22]	18411	1			T1	1280		T4	5		T26	1
valid_sources[0x23]	15623	1			T1	325		T4	9		T10	190
valid_sources[0x24]	16370	1			T1	164		T5	17		T4	10
valid_sources[0x25]	17240	1			T1	325		T5	2		T20	1
valid_sources[0x26]	14986	1			T1	240		T5	7		T10	6
valid_sources[0x27]	17146	1			T8	1		T1	369		T5	5
valid_sources[0x28]	15946	1			T1	365		T4	10		T26	1
valid_sources[0x29]	17104	1			T1	525		T5	1		T22	12
valid_sources[0x2a]	16956	1			T1	974		T5	5		T4	7
valid_sources[0x2b]	17802	1			T1	628		T5	5		T22	2
valid_sources[0x2c]	15633	1			T1	133		T5	5		T4	1
valid_sources[0x2d]	15415	1			T8	1		T1	443		T5	1
valid_sources[0x2e]	16695	1			T1	128		T4	6		T26	5
valid_sources[0x2f]	16124	1			T1	467		T4	3		T26	7
valid_sources[0x30]	16906	1			T1	262		T5	2		T4	2
valid_sources[0x31]	16558	1			T8	1		T1	3		T5	3
valid_sources[0x32]	17227	1			T8	1		T1	421		T5	19
valid_sources[0x33]	17498	1			T1	258		T4	2		T10	13
valid_sources[0x34]	15877	1			T8	1		T1	275		T4	4
valid_sources[0x35]	17438	1			T8	1		T1	284		T26	1
valid_sources[0x36]	17824	1			T1	249		T4	6		T10	346
valid_sources[0x37]	15835	1			T1	130		T4	5		T26	5
valid_sources[0x38]	16794	1			T1	139		T4	1		T26	2
valid_sources[0x39]	16366	1			T1	1201		T4	1		T26	3
valid_sources[0x3a]	16468	1			T1	1167		T5	2		T19	6
valid_sources[0x3b]	15060	1			T8	1		T1	492		T5	2
valid_sources[0x3c]	17304	1			T1	515		T5	13		T22	1
valid_sources[0x3d]	16191	1			T1	559		T26	3		T10	139
valid_sources[0x3e]	16690	1			T8	1		T1	502		T19	1
valid_sources[0x3f]	17382	1			T1	655		T26	4		T77	1
valid_sources[0x40]	18112	1			T8	1		T1	864		T5	2
valid_sources[0x41]	16248	1			T1	354		T4	5		T34	13
valid_sources[0x42]	16129	1			T1	431		T4	17		T26	1
valid_sources[0x43]	16353	1			T1	110		T21	1		T4	3
valid_sources[0x44]	18268	1			T1	452		T4	3		T26	1
valid_sources[0x45]	15908	1			T1	585		T4	2		T26	2
valid_sources[0x46]	16155	1			T1	297		T5	4		T4	7
valid_sources[0x47]	16287	1			T1	718		T10	5		T27	2
valid_sources[0x48]	16966	1			T1	595		T4	3		T26	1
valid_sources[0x49]	15941	1			T1	121		T5	3		T4	1
valid_sources[0x4a]	15980	1			T6	1		T8	2		T1	639
valid_sources[0x4b]	16267	1			T1	323		T34	11		T10	24
valid_sources[0x4c]	15503	1			T8	1		T1	10		T5	5
valid_sources[0x4d]	16971	1			T6	1		T1	383		T5	3
valid_sources[0x4e]	16951	1			T8	2		T1	909		T5	5
valid_sources[0x4f]	16315	1			T1	335		T20	1		T4	1
valid_sources[0x50]	14946	1			T1	592		T4	6		T26	3
valid_sources[0x51]	16839	1			T1	676		T4	6		T26	5
valid_sources[0x52]	15934	1			T1	32		T5	1		T4	3
valid_sources[0x53]	16667	1			T1	310		T5	1		T4	12
valid_sources[0x54]	17464	1			T8	1		T1	207		T5	2
valid_sources[0x55]	15599	1			T1	301		T20	1		T97	1
valid_sources[0x56]	15396	1			T8	1		T1	388		T4	1
valid_sources[0x57]	17204	1			T7	2		T8	1		T1	360
valid_sources[0x58]	16548	1			T1	456		T5	6		T4	11
valid_sources[0x59]	16966	1			T1	436		T4	5		T10	171
valid_sources[0x5a]	15775	1			T6	1		T1	385		T4	1
valid_sources[0x5b]	15803	1			T8	1		T1	552		T4	1
valid_sources[0x5c]	16092	1			T1	645		T21	1		T97	1
valid_sources[0x5d]	18008	1			T6	1		T1	419		T5	4
valid_sources[0x5e]	15856	1			T1	421		T26	8		T10	143
valid_sources[0x5f]	16641	1			T8	1		T1	206		T4	5
valid_sources[0x60]	16865	1			T8	1		T1	425		T4	8
valid_sources[0x61]	16756	1			T1	288		T4	1		T26	1
valid_sources[0x62]	14701	1			T1	388		T5	5		T4	10
valid_sources[0x63]	15950	1			T1	365		T5	4		T4	8
valid_sources[0x64]	17230	1			T1	710		T4	8		T26	1
valid_sources[0x65]	17072	1			T8	1		T1	1187		T26	3
valid_sources[0x66]	17287	1			T1	112		T5	4		T20	1
valid_sources[0x67]	16139	1			T1	753		T5	1		T10	175
valid_sources[0x68]	17774	1			T1	796		T4	3		T26	4
valid_sources[0x69]	17949	1			T8	1		T1	320		T5	6
valid_sources[0x6a]	15613	1			T1	154		T20	1		T4	14
valid_sources[0x6b]	17055	1			T1	831		T4	2		T26	8
valid_sources[0x6c]	17320	1			T1	342		T20	3		T21	1
valid_sources[0x6d]	15276	1			T1	463		T4	4		T26	6
valid_sources[0x6e]	15480	1			T1	312		T5	5		T19	2
valid_sources[0x6f]	16465	1			T1	651		T22	1		T26	10
valid_sources[0x70]	18344	1			T8	1		T1	434		T5	3
valid_sources[0x71]	17493	1			T8	1		T23	6		T1	155
valid_sources[0x72]	16888	1			T1	211		T5	1		T20	2
valid_sources[0x73]	17130	1			T1	463		T5	2		T22	2
valid_sources[0x74]	16154	1			T1	224		T4	7		T26	7
valid_sources[0x75]	18086	1			T1	421		T5	5		T4	3
valid_sources[0x76]	16851	1			T1	366		T26	5		T10	302
valid_sources[0x77]	16533	1			T1	664		T5	3		T26	2
valid_sources[0x78]	17267	1			T1	7		T20	1		T4	3
valid_sources[0x79]	16101	1			T6	2		T8	1		T1	196
valid_sources[0x7a]	16116	1			T1	126		T26	2		T10	189
valid_sources[0x7b]	16970	1			T6	3		T1	626		T22	2
valid_sources[0x7c]	16209	1			T1	463		T26	6		T77	4
valid_sources[0x7d]	17277	1			T7	14		T8	2		T1	315
valid_sources[0x7e]	18068	1			T1	530		T26	2		T10	375
valid_sources[0x7f]	16895	1			T8	1		T1	244		T26	2
valid_sources[0x80]	15990	1			T1	256		T20	1		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

918200

1

T7

18

T8

12

T23

1

values[0x0]

all_enables

biggest_size

1377963

1

T6

4

T7

1

T8

5

values[0x1]

all_enables

biggest_size

1333396

1

T6

2

T7

1

T8

4