SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[clkmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11651258 | 0 | T6 | 21 | T7 | 63 | T8 | 66 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11651061 | 1 | T6 | 21 | T7 | 63 | T8 | 66 | ||||
values[1] | 14 | 1 | T87 | 1 | T94 | 2 | T92 | 1 | ||||
values[2] | 4 | 1 | T87 | 1 | T95 | 1 | T150 | 1 | ||||
values[3] | 97 | 1 | T84 | 2 | T85 | 5 | T86 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11651065 | 1 | T6 | 21 | T7 | 63 | T8 | 66 | ||||
values[1] | 18 | 1 | T84 | 1 | T85 | 1 | T86 | 2 | ||||
values[2] | 5 | 1 | T84 | 2 | T95 | 1 | T151 | 1 | ||||
values[3] | 112 | 1 | T84 | 3 | T85 | 8 | T86 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 11650958 | 1 | T6 | 21 | T7 | 63 | T8 | 66 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T84 | 1 | T85 | 8 | T86 | 5 | ||||
auto[TlIntgErrData] | 103 | 1 | T84 | 7 | T85 | 9 | T86 | 8 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T84 | 2 | T85 | 3 | T86 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |