Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
302092 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
173259717 |
1 |
|
|
T6 |
720 |
|
T7 |
1171 |
|
T8 |
1215 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9349 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
173552460 |
1 |
|
|
T6 |
720 |
|
T7 |
1171 |
|
T8 |
1215 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
98899474 |
1 |
|
|
T6 |
722 |
|
T7 |
966 |
|
T8 |
1112 |
auto[1] |
74662335 |
1 |
|
|
T7 |
207 |
|
T8 |
105 |
|
T23 |
88 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5638 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T8 |
2 |
|
T1 |
10 |
|
T2 |
2 |
auto[0] |
auto[1] |
auto[0] |
244535 |
1 |
|
|
T1 |
252 |
|
T5 |
46 |
|
T21 |
64 |
auto[0] |
auto[1] |
auto[1] |
50371 |
1 |
|
|
T1 |
342 |
|
T5 |
24 |
|
T21 |
35 |
auto[1] |
auto[1] |
auto[0] |
98647138 |
1 |
|
|
T6 |
720 |
|
T7 |
964 |
|
T8 |
1112 |
auto[1] |
auto[1] |
auto[1] |
74610416 |
1 |
|
|
T7 |
207 |
|
T8 |
103 |
|
T23 |
88 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
155752 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
86623330 |
1 |
|
|
T6 |
359 |
|
T7 |
585 |
|
T8 |
602 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8272 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
86770810 |
1 |
|
|
T6 |
359 |
|
T7 |
585 |
|
T8 |
602 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49447879 |
1 |
|
|
T6 |
361 |
|
T7 |
484 |
|
T8 |
551 |
auto[1] |
37331203 |
1 |
|
|
T7 |
103 |
|
T8 |
53 |
|
T23 |
44 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5638 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T8 |
2 |
|
T1 |
10 |
|
T2 |
2 |
auto[0] |
auto[1] |
auto[0] |
121474 |
1 |
|
|
T1 |
123 |
|
T5 |
13 |
|
T21 |
28 |
auto[0] |
auto[1] |
auto[1] |
27092 |
1 |
|
|
T1 |
170 |
|
T5 |
18 |
|
T21 |
23 |
auto[1] |
auto[1] |
auto[0] |
49319681 |
1 |
|
|
T6 |
359 |
|
T7 |
482 |
|
T8 |
551 |
auto[1] |
auto[1] |
auto[1] |
37302563 |
1 |
|
|
T7 |
103 |
|
T8 |
51 |
|
T23 |
44 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
567522 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
346045607 |
1 |
|
|
T6 |
1441 |
|
T7 |
2345 |
|
T8 |
2078 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11500 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
346601629 |
1 |
|
|
T6 |
1441 |
|
T7 |
2345 |
|
T8 |
2078 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
197288540 |
1 |
|
|
T6 |
1443 |
|
T7 |
1933 |
|
T8 |
1869 |
auto[1] |
149324589 |
1 |
|
|
T7 |
414 |
|
T8 |
211 |
|
T23 |
176 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5638 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T8 |
2 |
|
T1 |
10 |
|
T2 |
2 |
auto[0] |
auto[1] |
auto[0] |
460235 |
1 |
|
|
T1 |
486 |
|
T5 |
71 |
|
T21 |
123 |
auto[0] |
auto[1] |
auto[1] |
100101 |
1 |
|
|
T1 |
666 |
|
T5 |
69 |
|
T21 |
76 |
auto[1] |
auto[1] |
auto[0] |
196818353 |
1 |
|
|
T6 |
1441 |
|
T7 |
1931 |
|
T8 |
1869 |
auto[1] |
auto[1] |
auto[1] |
149222940 |
1 |
|
|
T7 |
414 |
|
T8 |
209 |
|
T23 |
176 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
296840 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
177737550 |
1 |
|
|
T6 |
720 |
|
T7 |
1172 |
|
T8 |
1038 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9119 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
178025271 |
1 |
|
|
T6 |
720 |
|
T7 |
1172 |
|
T8 |
1038 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
101273574 |
1 |
|
|
T6 |
722 |
|
T7 |
967 |
|
T8 |
935 |
auto[1] |
76760816 |
1 |
|
|
T7 |
207 |
|
T8 |
105 |
|
T23 |
88 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5626 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1560 |
1 |
|
|
T8 |
2 |
|
T1 |
10 |
|
T2 |
2 |
auto[0] |
auto[1] |
auto[0] |
236171 |
1 |
|
|
T1 |
229 |
|
T5 |
34 |
|
T21 |
58 |
auto[0] |
auto[1] |
auto[1] |
53483 |
1 |
|
|
T1 |
327 |
|
T5 |
36 |
|
T21 |
40 |
auto[1] |
auto[1] |
auto[0] |
101029844 |
1 |
|
|
T6 |
720 |
|
T7 |
965 |
|
T8 |
935 |
auto[1] |
auto[1] |
auto[1] |
76705773 |
1 |
|
|
T7 |
207 |
|
T8 |
103 |
|
T23 |
88 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |