Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T21
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T17,T18,T32
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	787303507	12427	0	0
GateOpen_A	787303507	19444	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787303507	12427	0	0
T1	1673455	125	0	0
T2	536313	0	0	0
T4	258568	0	0	0
T5	338461	26	0	0
T10	0	201	0	0
T11	0	17	0	0
T17	42738	16	0	0
T18	2492	3	0	0
T19	4329	0	0	0
T20	37989	0	0	0
T21	4646	38	0	0
T22	21507	0	0	0
T32	0	12	0	0
T33	0	22	0	0
T34	0	4	0	0
T103	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787303507	19444	0	0
T1	1673455	145	0	0
T2	536313	0	0	0
T5	338461	34	0	0
T6	3432	4	0	0
T7	5755	4	0	0
T8	5332	0	0	0
T17	42738	20	0	0
T18	2492	7	0	0
T19	4329	0	0	0
T20	0	4	0	0
T21	0	38	0	0
T22	0	4	0	0
T23	5434	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T21
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T17,T18,T32
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	86666959	2942	0	0
GateOpen_A	86666959	4695	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666959	2942	0	0
T1	926899	32	0	0
T2	59577	0	0	0
T4	17756	0	0	0
T5	34686	6	0	0
T10	0	51	0	0
T17	4737	3	0	0
T18	259	1	0	0
T19	496	0	0	0
T20	3566	0	0	0
T21	494	8	0	0
T22	2619	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666959	4695	0	0
T1	926899	37	0	0
T2	59577	0	0	0
T5	34686	8	0	0
T6	368	1	0	0
T7	622	1	0	0
T8	635	0	0	0
T17	4737	4	0	0
T18	259	2	0	0
T19	496	0	0	0
T20	0	1	0	0
T21	0	8	0	0
T22	0	1	0	0
T23	597	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T21
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T17,T18,T32
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	173334766	3164	0	0
GateOpen_A	173334766	4917	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334766	3164	0	0
T1	185381	31	0	0
T2	119153	0	0	0
T4	35507	0	0	0
T5	69372	7	0	0
T10	0	50	0	0
T17	9474	3	0	0
T18	517	1	0	0
T19	991	0	0	0
T20	7131	0	0	0
T21	988	12	0	0
T22	5243	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334766	4917	0	0
T1	185381	36	0	0
T2	119153	0	0	0
T5	69372	9	0	0
T6	736	1	0	0
T7	1243	1	0	0
T8	1272	0	0	0
T17	9474	4	0	0
T18	517	2	0	0
T19	991	0	0	0
T20	0	1	0	0
T21	0	12	0	0
T22	0	1	0	0
T23	1194	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T21
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T17,T18,T32
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	348369730	3169	0	0
GateOpen_A	348369730	4924	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369730	3169	0	0
T1	371423	32	0	0
T2	238385	0	0	0
T4	136868	0	0	0
T5	138986	6	0	0
T10	0	51	0	0
T17	18973	3	0	0
T18	1141	1	0	0
T19	1895	0	0	0
T20	14355	0	0	0
T21	2109	9	0	0
T22	9097	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369730	4924	0	0
T1	371423	37	0	0
T2	238385	0	0	0
T5	138986	8	0	0
T6	1552	1	0	0
T7	2593	1	0	0
T8	2283	0	0	0
T17	18973	4	0	0
T18	1141	2	0	0
T19	1895	0	0	0
T20	0	1	0	0
T21	0	9	0	0
T22	0	1	0	0
T23	2429	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T21
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T17,T32,T33
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	178932052	3152	0	0
GateOpen_A	178932052	4908	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178932052	3152	0	0
T1	189752	30	0	0
T2	119198	0	0	0
T4	68437	0	0	0
T5	95417	7	0	0
T10	0	49	0	0
T11	0	17	0	0
T17	9554	7	0	0
T18	575	0	0	0
T19	947	0	0	0
T20	12937	0	0	0
T21	1055	9	0	0
T22	4548	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T103	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178932052	4908	0	0
T1	189752	35	0	0
T2	119198	0	0	0
T5	95417	9	0	0
T6	776	1	0	0
T7	1297	1	0	0
T8	1142	0	0	0
T17	9554	8	0	0
T18	575	1	0	0
T19	947	0	0	0
T20	0	1	0	0
T21	0	9	0	0
T22	0	1	0	0
T23	1214	1	0	0