Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	819626855	82914	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819626855	82914	0	0
T1	1983525	1283	0	0
T2	620810	189	0	0
T3	0	46	0	0
T4	684335	0	0	0
T5	964120	0	0	0
T10	0	334	0	0
T11	0	181	0	0
T12	0	237	0	0
T13	0	1209	0	0
T14	0	277	0	0
T15	0	1360	0	0
T16	0	783	0	0
T17	5670	0	0	0
T18	5985	0	0	0
T19	9470	0	0	0
T20	36385	0	0	0
T21	5820	0	0	0
T22	11840	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163925371	11963	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	11963	0	0
T1	396705	168	0	0
T2	124162	27	0	0
T3	0	7	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	53	0	0
T11	0	24	0	0
T12	0	39	0	0
T13	0	159	0	0
T14	0	44	0	0
T15	0	173	0	0
T16	0	113	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163925371	11799	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	11799	0	0
T1	396705	164	0	0
T2	124162	26	0	0
T3	0	7	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	53	0	0
T11	0	23	0	0
T12	0	38	0	0
T13	0	154	0	0
T14	0	43	0	0
T15	0	197	0	0
T16	0	112	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163925371	16640	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	16640	0	0
T1	396705	257	0	0
T2	124162	38	0	0
T3	0	9	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	67	0	0
T11	0	37	0	0
T12	0	48	0	0
T13	0	243	0	0
T14	0	56	0	0
T15	0	269	0	0
T16	0	156	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163925371	16676	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	16676	0	0
T1	396705	261	0	0
T2	124162	38	0	0
T3	0	9	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	67	0	0
T11	0	37	0	0
T12	0	47	0	0
T13	0	247	0	0
T14	0	56	0	0
T15	0	270	0	0
T16	0	158	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163925371	25836	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	25836	0	0
T1	396705	433	0	0
T2	124162	60	0	0
T3	0	14	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	94	0	0
T11	0	60	0	0
T12	0	65	0	0
T13	0	406	0	0
T14	0	78	0	0
T15	0	451	0	0
T16	0	244	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0