Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T5,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	163925371	161141961	0	0
AllClkBypReqTrue_A	163925371	133706	0	0
IoClkBypReqFalse_A	163925371	161058411	0	2415
IoClkBypReqTrue_A	163925371	212400	0	0
LcClkBypAckFalse_A	163925371	161151031	0	0
LcClkBypAckTrue_A	163925371	124636	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	161141961	0	0
T1	396705	394349	0	0
T2	124162	124098	0	0
T5	192824	192395	0	0
T6	1551	1442	0	0
T7	2620	2372	0	0
T8	2355	1997	0	0
T17	1134	1127	0	0
T18	1197	1013	0	0
T19	1894	1634	0	0
T23	1214	1068	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	133706	0	0
T1	396705	1489	0	0
T2	124162	0	0	0
T5	192824	0	0	0
T8	2355	147	0	0
T10	0	1614	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	138	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	0	313	0	0
T23	1214	23	0	0
T77	0	127	0	0
T97	0	112	0	0
T98	0	71	0	0
T99	0	96	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	161058411	0	2415
T1	396705	394251	0	3
T2	124162	124096	0	3
T5	192824	192389	0	3
T6	1551	1440	0	3
T7	2620	2370	0	3
T8	2355	1790	0	3
T17	1134	1125	0	3
T18	1197	1011	0	3
T19	1894	1770	0	3
T23	1214	1016	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	212400	0	0
T1	396705	2454	0	0
T2	124162	0	0	0
T5	192824	0	0	0
T8	2355	352	0	0
T10	0	1989	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	0	516	0	0
T23	1214	73	0	0
T77	0	222	0	0
T78	0	120	0	0
T97	0	325	0	0
T98	0	137	0	0
T100	0	329	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	161151031	0	0
T1	396705	394355	0	0
T2	124162	124098	0	0
T5	192824	192395	0	0
T6	1551	1442	0	0
T7	2620	2372	0	0
T8	2355	1996	0	0
T17	1134	1127	0	0
T18	1197	1013	0	0
T19	1894	1772	0	0
T23	1214	1056	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	124636	0	0
T1	396705	1430	0	0
T2	124162	0	0	0
T5	192824	0	0	0
T8	2355	148	0	0
T10	0	1463	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	0	193	0	0
T23	1214	35	0	0
T77	0	106	0	0
T78	0	40	0	0
T97	0	184	0	0
T98	0	76	0	0
T100	0	240	0	0