Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1491230388	13981	0	0
TransStop_A	1491230388	7279	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1491230388	13981	0	0
T1	1586048	179	0	0
T2	993304	0	0	0
T5	723128	32	0	0
T7	10804	17	0	0
T8	9516	0	0	0
T10	0	111	0	0
T11	0	76	0	0
T17	80740	0	0	0
T18	4792	0	0	0
T19	7896	0	0	0
T20	107812	0	0	0
T23	10120	0	0	0
T34	0	4	0	0
T101	0	3	0	0
T102	0	23	0	0
T103	0	4	0	0
T104	0	25	0	0
T105	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1491230388	7279	0	0
T1	1586048	99	0	0
T2	993304	0	0	0
T5	723128	18	0	0
T7	10804	11	0	0
T8	9516	0	0	0
T10	0	56	0	0
T11	0	44	0	0
T17	80740	0	0	0
T18	4792	0	0	0
T19	7896	0	0	0
T20	107812	0	0	0
T23	10120	0	0	0
T34	0	4	0	0
T101	0	3	0	0
T102	0	13	0	0
T103	0	4	0	0
T104	0	14	0	0
T106	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	372807597	3439	0	0
TransStop_A	372807597	1809	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	3439	0	0
T1	396512	40	0	0
T2	248326	0	0	0
T5	180782	8	0	0
T7	2701	6	0	0
T8	2379	0	0	0
T10	0	25	0	0
T11	0	18	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0
T103	0	1	0	0
T104	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	1809	0	0
T1	396512	19	0	0
T2	248326	0	0	0
T5	180782	5	0	0
T7	2701	4	0	0
T8	2379	0	0	0
T10	0	10	0	0
T11	0	12	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	3	0	0
T103	0	1	0	0
T104	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	372807597	3472	0	0
TransStop_A	372807597	1794	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	3472	0	0
T1	396512	49	0	0
T2	248326	0	0	0
T5	180782	8	0	0
T7	2701	5	0	0
T8	2379	0	0	0
T10	0	33	0	0
T11	0	17	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0
T103	0	1	0	0
T104	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	1794	0	0
T1	396512	27	0	0
T2	248326	0	0	0
T5	180782	4	0	0
T7	2701	4	0	0
T8	2379	0	0	0
T10	0	18	0	0
T11	0	10	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	3	0	0
T103	0	1	0	0
T104	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	372807597	3626	0	0
TransStop_A	372807597	1879	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	3626	0	0
T1	396512	42	0	0
T2	248326	0	0	0
T5	180782	6	0	0
T7	2701	3	0	0
T8	2379	0	0	0
T10	0	25	0	0
T11	0	20	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	6	0	0
T103	0	1	0	0
T104	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	1879	0	0
T1	396512	26	0	0
T2	248326	0	0	0
T5	180782	4	0	0
T7	2701	2	0	0
T8	2379	0	0	0
T10	0	14	0	0
T11	0	10	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	4	0	0
T103	0	1	0	0
T104	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	372807597	3444	0	0
TransStop_A	372807597	1797	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	3444	0	0
T1	396512	48	0	0
T2	248326	0	0	0
T5	180782	10	0	0
T7	2701	3	0	0
T8	2379	0	0	0
T10	0	28	0	0
T11	0	21	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T102	0	7	0	0
T103	0	1	0	0
T104	0	6	0	0
T105	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807597	1797	0	0
T1	396512	27	0	0
T2	248326	0	0	0
T5	180782	5	0	0
T7	2701	1	0	0
T8	2379	0	0	0
T10	0	14	0	0
T11	0	12	0	0
T17	20185	0	0	0
T18	1198	0	0	0
T19	1974	0	0	0
T20	26953	0	0	0
T23	2530	0	0	0
T34	0	1	0	0
T102	0	3	0	0
T103	0	1	0	0
T104	0	3	0	0
T106	0	1	0	0