Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	163925371	19338905	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	19338905	0	58
T1	396705	159120	0	0
T2	124162	18945	0	1
T3	0	5382	0	1
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	25141	0	0
T11	0	24044	0	0
T12	0	15261	0	1
T13	0	142331	0	0
T14	0	19973	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T24	0	961	0	1
T25	0	878	0	1
T67	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1
T110	0	0	0	1