Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
903670 |
0 |
0 |
T1 |
2647681 |
4909 |
0 |
0 |
T2 |
1027903 |
562 |
0 |
0 |
T3 |
0 |
138 |
0 |
0 |
T4 |
540584 |
200 |
0 |
0 |
T5 |
755393 |
764 |
0 |
0 |
T10 |
0 |
4013 |
0 |
0 |
T11 |
0 |
976 |
0 |
0 |
T12 |
0 |
288 |
0 |
0 |
T17 |
73449 |
0 |
0 |
0 |
T18 |
5343 |
0 |
0 |
0 |
T19 |
9231 |
0 |
0 |
0 |
T20 |
73538 |
72 |
0 |
0 |
T21 |
8928 |
0 |
0 |
0 |
T22 |
39288 |
0 |
0 |
0 |
T24 |
0 |
188 |
0 |
0 |
T26 |
0 |
150 |
0 |
0 |
T27 |
0 |
181 |
0 |
0 |
T49 |
20670 |
2 |
0 |
0 |
T51 |
3979 |
2 |
0 |
0 |
T52 |
18386 |
1 |
0 |
0 |
T53 |
16134 |
2 |
0 |
0 |
T54 |
12928 |
3 |
0 |
0 |
T55 |
3758 |
0 |
0 |
0 |
T57 |
4250 |
1 |
0 |
0 |
T58 |
18890 |
1 |
0 |
0 |
T59 |
15256 |
2 |
0 |
0 |
T105 |
0 |
372 |
0 |
0 |
T111 |
27086 |
0 |
0 |
0 |
T112 |
19310 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
902560 |
0 |
0 |
T1 |
1643551 |
4912 |
0 |
0 |
T2 |
369508 |
562 |
0 |
0 |
T3 |
0 |
138 |
0 |
0 |
T4 |
310461 |
200 |
0 |
0 |
T5 |
457256 |
764 |
0 |
0 |
T10 |
0 |
4013 |
0 |
0 |
T11 |
0 |
976 |
0 |
0 |
T12 |
0 |
288 |
0 |
0 |
T17 |
18098 |
0 |
0 |
0 |
T18 |
3243 |
0 |
0 |
0 |
T19 |
5327 |
0 |
0 |
0 |
T20 |
21904 |
72 |
0 |
0 |
T21 |
3928 |
0 |
0 |
0 |
T22 |
12631 |
0 |
0 |
0 |
T24 |
0 |
188 |
0 |
0 |
T26 |
0 |
150 |
0 |
0 |
T27 |
0 |
181 |
0 |
0 |
T49 |
8238 |
2 |
0 |
0 |
T51 |
15319 |
2 |
0 |
0 |
T52 |
16906 |
1 |
0 |
0 |
T53 |
14368 |
2 |
0 |
0 |
T54 |
102072 |
3 |
0 |
0 |
T55 |
6793 |
0 |
0 |
0 |
T57 |
33062 |
1 |
0 |
0 |
T58 |
34354 |
1 |
0 |
0 |
T59 |
43962 |
2 |
0 |
0 |
T105 |
0 |
372 |
0 |
0 |
T111 |
11128 |
0 |
0 |
0 |
T112 |
17770 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
351218874 |
24008 |
0 |
0 |
T1 |
371423 |
282 |
0 |
0 |
T2 |
238384 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
138985 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
18972 |
0 |
0 |
0 |
T18 |
1140 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
14354 |
4 |
0 |
0 |
T21 |
2109 |
0 |
0 |
0 |
T22 |
9096 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
24008 |
0 |
0 |
T1 |
396705 |
282 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
351218874 |
30459 |
0 |
0 |
T1 |
371423 |
293 |
0 |
0 |
T2 |
238384 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
138985 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
18972 |
0 |
0 |
0 |
T18 |
1140 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
14354 |
4 |
0 |
0 |
T21 |
2109 |
0 |
0 |
0 |
T22 |
9096 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30473 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30443 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
351218874 |
30462 |
0 |
0 |
T1 |
371423 |
293 |
0 |
0 |
T2 |
238384 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
138985 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
18972 |
0 |
0 |
0 |
T18 |
1140 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
14354 |
4 |
0 |
0 |
T21 |
2109 |
0 |
0 |
0 |
T22 |
9096 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174712227 |
24008 |
0 |
0 |
T1 |
185381 |
282 |
0 |
0 |
T2 |
119152 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
35507 |
40 |
0 |
0 |
T5 |
69372 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
9474 |
0 |
0 |
0 |
T18 |
517 |
0 |
0 |
0 |
T19 |
991 |
0 |
0 |
0 |
T20 |
7130 |
4 |
0 |
0 |
T21 |
988 |
0 |
0 |
0 |
T22 |
5243 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
24008 |
0 |
0 |
T1 |
396705 |
282 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174712227 |
30557 |
0 |
0 |
T1 |
185381 |
293 |
0 |
0 |
T2 |
119152 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
35507 |
80 |
0 |
0 |
T5 |
69372 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
9474 |
0 |
0 |
0 |
T18 |
517 |
0 |
0 |
0 |
T19 |
991 |
0 |
0 |
0 |
T20 |
7130 |
4 |
0 |
0 |
T21 |
988 |
0 |
0 |
0 |
T22 |
5243 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30586 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30551 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174712227 |
30559 |
0 |
0 |
T1 |
185381 |
293 |
0 |
0 |
T2 |
119152 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
35507 |
80 |
0 |
0 |
T5 |
69372 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
9474 |
0 |
0 |
0 |
T18 |
517 |
0 |
0 |
0 |
T19 |
991 |
0 |
0 |
0 |
T20 |
7130 |
4 |
0 |
0 |
T21 |
988 |
0 |
0 |
0 |
T22 |
5243 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87355486 |
24008 |
0 |
0 |
T1 |
926898 |
282 |
0 |
0 |
T2 |
59576 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
17755 |
40 |
0 |
0 |
T5 |
34686 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
4737 |
0 |
0 |
0 |
T18 |
258 |
0 |
0 |
0 |
T19 |
496 |
0 |
0 |
0 |
T20 |
3565 |
4 |
0 |
0 |
T21 |
494 |
0 |
0 |
0 |
T22 |
2619 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
24008 |
0 |
0 |
T1 |
396705 |
282 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87355486 |
30435 |
0 |
0 |
T1 |
926898 |
293 |
0 |
0 |
T2 |
59576 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
17755 |
80 |
0 |
0 |
T5 |
34686 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
4737 |
0 |
0 |
0 |
T18 |
258 |
0 |
0 |
0 |
T19 |
496 |
0 |
0 |
0 |
T20 |
3565 |
4 |
0 |
0 |
T21 |
494 |
0 |
0 |
0 |
T22 |
2619 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30470 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30433 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87355486 |
30441 |
0 |
0 |
T1 |
926898 |
293 |
0 |
0 |
T2 |
59576 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
17755 |
80 |
0 |
0 |
T5 |
34686 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
4737 |
0 |
0 |
0 |
T18 |
258 |
0 |
0 |
0 |
T19 |
496 |
0 |
0 |
0 |
T20 |
3565 |
4 |
0 |
0 |
T21 |
494 |
0 |
0 |
0 |
T22 |
2619 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375775600 |
24008 |
0 |
0 |
T1 |
396512 |
282 |
0 |
0 |
T2 |
248325 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
142574 |
40 |
0 |
0 |
T5 |
180782 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
20184 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1974 |
0 |
0 |
0 |
T20 |
26952 |
4 |
0 |
0 |
T21 |
2197 |
0 |
0 |
0 |
T22 |
9476 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
24008 |
0 |
0 |
T1 |
396705 |
282 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375775600 |
30423 |
0 |
0 |
T1 |
396512 |
293 |
0 |
0 |
T2 |
248325 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
142574 |
80 |
0 |
0 |
T5 |
180782 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
20184 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1974 |
0 |
0 |
0 |
T20 |
26952 |
4 |
0 |
0 |
T21 |
2197 |
0 |
0 |
0 |
T22 |
9476 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30441 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30414 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375775600 |
30429 |
0 |
0 |
T1 |
396512 |
293 |
0 |
0 |
T2 |
248325 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
142574 |
80 |
0 |
0 |
T5 |
180782 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
20184 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1974 |
0 |
0 |
0 |
T20 |
26952 |
4 |
0 |
0 |
T21 |
2197 |
0 |
0 |
0 |
T22 |
9476 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180356478 |
23554 |
0 |
0 |
T1 |
189752 |
282 |
0 |
0 |
T2 |
119198 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
68437 |
20 |
0 |
0 |
T5 |
95417 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
9554 |
0 |
0 |
0 |
T18 |
574 |
0 |
0 |
0 |
T19 |
947 |
0 |
0 |
0 |
T20 |
12937 |
4 |
0 |
0 |
T21 |
1055 |
0 |
0 |
0 |
T22 |
4548 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
18 |
0 |
0 |
T27 |
0 |
28 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
24008 |
0 |
0 |
T1 |
396705 |
282 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
40 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
194 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
30 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180356478 |
30508 |
0 |
0 |
T1 |
189752 |
293 |
0 |
0 |
T2 |
119198 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
68437 |
70 |
0 |
0 |
T5 |
95417 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
9554 |
0 |
0 |
0 |
T18 |
574 |
0 |
0 |
0 |
T19 |
947 |
0 |
0 |
0 |
T20 |
12937 |
4 |
0 |
0 |
T21 |
1055 |
0 |
0 |
0 |
T22 |
4548 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
59 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30702 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
80 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
30397 |
0 |
0 |
T1 |
396705 |
293 |
0 |
0 |
T2 |
124162 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
136867 |
67 |
0 |
0 |
T5 |
192824 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
4 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
2368 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
58 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180356478 |
30539 |
0 |
0 |
T1 |
189752 |
293 |
0 |
0 |
T2 |
119198 |
42 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
68437 |
72 |
0 |
0 |
T5 |
95417 |
32 |
0 |
0 |
T10 |
0 |
199 |
0 |
0 |
T17 |
9554 |
0 |
0 |
0 |
T18 |
574 |
0 |
0 |
0 |
T19 |
947 |
0 |
0 |
0 |
T20 |
12937 |
4 |
0 |
0 |
T21 |
1055 |
0 |
0 |
0 |
T22 |
4548 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T26 |
0 |
60 |
0 |
0 |
T27 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T54,T112,T113 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T54,T112,T113 |
1 | 1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
39 |
0 |
0 |
T51 |
3979 |
2 |
0 |
0 |
T52 |
9193 |
2 |
0 |
0 |
T53 |
8067 |
3 |
0 |
0 |
T54 |
6464 |
3 |
0 |
0 |
T111 |
13543 |
1 |
0 |
0 |
T112 |
9655 |
2 |
0 |
0 |
T114 |
4836 |
1 |
0 |
0 |
T115 |
6724 |
1 |
0 |
0 |
T116 |
8164 |
1 |
0 |
0 |
T117 |
6285 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
351218874 |
39 |
0 |
0 |
T51 |
31835 |
2 |
0 |
0 |
T52 |
18386 |
2 |
0 |
0 |
T53 |
16134 |
3 |
0 |
0 |
T54 |
103430 |
3 |
0 |
0 |
T111 |
13001 |
1 |
0 |
0 |
T112 |
19309 |
2 |
0 |
0 |
T114 |
9284 |
1 |
0 |
0 |
T115 |
6724 |
1 |
0 |
0 |
T116 |
8078 |
1 |
0 |
0 |
T117 |
16759 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T52 |
1 | 0 | Covered | T49,T51,T52 |
1 | 1 | Covered | T51,T58,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T52 |
1 | 0 | Covered | T51,T58,T54 |
1 | 1 | Covered | T49,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
39 |
0 |
0 |
T49 |
10335 |
2 |
0 |
0 |
T51 |
3979 |
4 |
0 |
0 |
T52 |
9193 |
2 |
0 |
0 |
T53 |
8067 |
2 |
0 |
0 |
T54 |
6464 |
3 |
0 |
0 |
T58 |
9445 |
2 |
0 |
0 |
T111 |
13543 |
1 |
0 |
0 |
T112 |
9655 |
1 |
0 |
0 |
T114 |
4836 |
2 |
0 |
0 |
T115 |
6724 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
351218874 |
39 |
0 |
0 |
T49 |
10228 |
2 |
0 |
0 |
T51 |
31835 |
4 |
0 |
0 |
T52 |
18386 |
2 |
0 |
0 |
T53 |
16134 |
2 |
0 |
0 |
T54 |
103430 |
3 |
0 |
0 |
T58 |
36269 |
2 |
0 |
0 |
T111 |
13001 |
1 |
0 |
0 |
T112 |
19309 |
1 |
0 |
0 |
T114 |
9284 |
2 |
0 |
0 |
T115 |
6724 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T52 |
1 | 0 | Covered | T49,T51,T52 |
1 | 1 | Covered | T54,T111,T118 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T52 |
1 | 0 | Covered | T54,T111,T118 |
1 | 1 | Covered | T49,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
41 |
0 |
0 |
T49 |
10335 |
2 |
0 |
0 |
T51 |
3979 |
2 |
0 |
0 |
T52 |
9193 |
1 |
0 |
0 |
T53 |
8067 |
2 |
0 |
0 |
T54 |
6464 |
3 |
0 |
0 |
T57 |
2125 |
1 |
0 |
0 |
T58 |
9445 |
1 |
0 |
0 |
T59 |
7628 |
2 |
0 |
0 |
T111 |
13543 |
4 |
0 |
0 |
T112 |
9655 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174712227 |
41 |
0 |
0 |
T49 |
4119 |
2 |
0 |
0 |
T51 |
15319 |
2 |
0 |
0 |
T52 |
8453 |
1 |
0 |
0 |
T53 |
7184 |
2 |
0 |
0 |
T54 |
51036 |
3 |
0 |
0 |
T57 |
16531 |
1 |
0 |
0 |
T58 |
17177 |
1 |
0 |
0 |
T59 |
21981 |
2 |
0 |
0 |
T111 |
5564 |
4 |
0 |
0 |
T112 |
8885 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T52,T57 |
1 | 0 | Covered | T49,T52,T57 |
1 | 1 | Covered | T53,T111,T119 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T52,T57 |
1 | 0 | Covered | T53,T111,T119 |
1 | 1 | Covered | T49,T52,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
38 |
0 |
0 |
T49 |
10335 |
2 |
0 |
0 |
T52 |
9193 |
1 |
0 |
0 |
T53 |
8067 |
3 |
0 |
0 |
T54 |
6464 |
1 |
0 |
0 |
T55 |
3758 |
1 |
0 |
0 |
T57 |
2125 |
1 |
0 |
0 |
T58 |
9445 |
1 |
0 |
0 |
T59 |
7628 |
2 |
0 |
0 |
T111 |
13543 |
3 |
0 |
0 |
T112 |
9655 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174712227 |
38 |
0 |
0 |
T49 |
4119 |
2 |
0 |
0 |
T52 |
8453 |
1 |
0 |
0 |
T53 |
7184 |
3 |
0 |
0 |
T54 |
51036 |
1 |
0 |
0 |
T55 |
6793 |
1 |
0 |
0 |
T57 |
16531 |
1 |
0 |
0 |
T58 |
17177 |
1 |
0 |
0 |
T59 |
21981 |
2 |
0 |
0 |
T111 |
5564 |
3 |
0 |
0 |
T112 |
8885 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T57,T58 |
1 | 0 | Covered | T49,T57,T58 |
1 | 1 | Covered | T54,T120 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T57,T58 |
1 | 0 | Covered | T54,T120 |
1 | 1 | Covered | T49,T57,T58 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
31 |
0 |
0 |
T49 |
10335 |
1 |
0 |
0 |
T53 |
8067 |
1 |
0 |
0 |
T54 |
6464 |
3 |
0 |
0 |
T55 |
3758 |
1 |
0 |
0 |
T57 |
2125 |
1 |
0 |
0 |
T58 |
9445 |
2 |
0 |
0 |
T59 |
7628 |
2 |
0 |
0 |
T73 |
7877 |
1 |
0 |
0 |
T111 |
13543 |
2 |
0 |
0 |
T112 |
9655 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87355486 |
31 |
0 |
0 |
T49 |
2059 |
1 |
0 |
0 |
T53 |
3591 |
1 |
0 |
0 |
T54 |
25518 |
3 |
0 |
0 |
T55 |
3396 |
1 |
0 |
0 |
T57 |
8266 |
1 |
0 |
0 |
T58 |
8590 |
2 |
0 |
0 |
T59 |
10991 |
2 |
0 |
0 |
T73 |
3742 |
1 |
0 |
0 |
T111 |
2779 |
2 |
0 |
0 |
T112 |
4443 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T57 |
1 | 0 | Covered | T49,T51,T57 |
1 | 1 | Covered | T54,T120,T121 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T51,T57 |
1 | 0 | Covered | T54,T120,T121 |
1 | 1 | Covered | T49,T51,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
36 |
0 |
0 |
T49 |
10335 |
1 |
0 |
0 |
T51 |
3979 |
1 |
0 |
0 |
T53 |
8067 |
1 |
0 |
0 |
T54 |
6464 |
3 |
0 |
0 |
T55 |
3758 |
1 |
0 |
0 |
T57 |
2125 |
1 |
0 |
0 |
T58 |
9445 |
2 |
0 |
0 |
T59 |
7628 |
1 |
0 |
0 |
T111 |
13543 |
3 |
0 |
0 |
T114 |
4836 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
87355486 |
36 |
0 |
0 |
T49 |
2059 |
1 |
0 |
0 |
T51 |
7659 |
1 |
0 |
0 |
T53 |
3591 |
1 |
0 |
0 |
T54 |
25518 |
3 |
0 |
0 |
T55 |
3396 |
1 |
0 |
0 |
T57 |
8266 |
1 |
0 |
0 |
T58 |
8590 |
2 |
0 |
0 |
T59 |
10991 |
1 |
0 |
0 |
T111 |
2779 |
3 |
0 |
0 |
T114 |
1958 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T50,T52,T59 |
1 | 0 | Covered | T50,T52,T59 |
1 | 1 | Covered | T120 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T50,T52,T59 |
1 | 0 | Covered | T120 |
1 | 1 | Covered | T50,T52,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
25 |
0 |
0 |
T50 |
6239 |
2 |
0 |
0 |
T52 |
9193 |
2 |
0 |
0 |
T53 |
8067 |
1 |
0 |
0 |
T54 |
6464 |
2 |
0 |
0 |
T59 |
7628 |
2 |
0 |
0 |
T112 |
9655 |
1 |
0 |
0 |
T114 |
4836 |
1 |
0 |
0 |
T120 |
11483 |
2 |
0 |
0 |
T122 |
12044 |
1 |
0 |
0 |
T123 |
10087 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375775600 |
25 |
0 |
0 |
T50 |
24960 |
2 |
0 |
0 |
T52 |
19153 |
2 |
0 |
0 |
T53 |
16807 |
1 |
0 |
0 |
T54 |
107744 |
2 |
0 |
0 |
T59 |
47680 |
2 |
0 |
0 |
T112 |
20114 |
1 |
0 |
0 |
T114 |
9672 |
1 |
0 |
0 |
T120 |
45934 |
2 |
0 |
0 |
T122 |
50185 |
1 |
0 |
0 |
T123 |
59339 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T52 |
1 | 0 | Covered | T49,T50,T52 |
1 | 1 | Covered | T59,T53,T124 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T52 |
1 | 0 | Covered | T59,T53,T124 |
1 | 1 | Covered | T49,T50,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
29 |
0 |
0 |
T49 |
10335 |
1 |
0 |
0 |
T50 |
6239 |
4 |
0 |
0 |
T52 |
9193 |
1 |
0 |
0 |
T53 |
8067 |
2 |
0 |
0 |
T54 |
6464 |
2 |
0 |
0 |
T57 |
2125 |
1 |
0 |
0 |
T58 |
9445 |
1 |
0 |
0 |
T59 |
7628 |
2 |
0 |
0 |
T112 |
9655 |
1 |
0 |
0 |
T114 |
4836 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375775600 |
29 |
0 |
0 |
T49 |
10655 |
1 |
0 |
0 |
T50 |
24960 |
4 |
0 |
0 |
T52 |
19153 |
1 |
0 |
0 |
T53 |
16807 |
2 |
0 |
0 |
T54 |
107744 |
2 |
0 |
0 |
T57 |
35432 |
1 |
0 |
0 |
T58 |
37782 |
1 |
0 |
0 |
T59 |
47680 |
2 |
0 |
0 |
T112 |
20114 |
1 |
0 |
0 |
T114 |
9672 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T56 |
1 | 0 | Covered | T49,T50,T56 |
1 | 1 | Covered | T49,T112,T122 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T56 |
1 | 0 | Covered | T49,T112,T122 |
1 | 1 | Covered | T49,T50,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
45 |
0 |
0 |
T49 |
10335 |
4 |
0 |
0 |
T50 |
6239 |
2 |
0 |
0 |
T53 |
8067 |
1 |
0 |
0 |
T56 |
5517 |
2 |
0 |
0 |
T59 |
7628 |
1 |
0 |
0 |
T111 |
13543 |
3 |
0 |
0 |
T112 |
9655 |
3 |
0 |
0 |
T115 |
6724 |
2 |
0 |
0 |
T117 |
6285 |
2 |
0 |
0 |
T120 |
11483 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180356478 |
45 |
0 |
0 |
T49 |
5114 |
4 |
0 |
0 |
T50 |
11981 |
2 |
0 |
0 |
T53 |
8067 |
1 |
0 |
0 |
T56 |
5517 |
2 |
0 |
0 |
T59 |
22886 |
1 |
0 |
0 |
T111 |
6501 |
3 |
0 |
0 |
T112 |
9655 |
3 |
0 |
0 |
T115 |
3362 |
2 |
0 |
0 |
T117 |
8380 |
2 |
0 |
0 |
T120 |
22048 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T56 |
1 | 0 | Covered | T49,T50,T56 |
1 | 1 | Covered | T49,T122,T121 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T49,T50,T56 |
1 | 0 | Covered | T49,T122,T121 |
1 | 1 | Covered | T49,T50,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164868292 |
34 |
0 |
0 |
T49 |
10335 |
5 |
0 |
0 |
T50 |
6239 |
1 |
0 |
0 |
T53 |
8067 |
2 |
0 |
0 |
T56 |
5517 |
1 |
0 |
0 |
T59 |
7628 |
1 |
0 |
0 |
T111 |
13543 |
1 |
0 |
0 |
T112 |
9655 |
1 |
0 |
0 |
T115 |
6724 |
2 |
0 |
0 |
T116 |
8164 |
1 |
0 |
0 |
T117 |
6285 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
180356478 |
34 |
0 |
0 |
T49 |
5114 |
5 |
0 |
0 |
T50 |
11981 |
1 |
0 |
0 |
T53 |
8067 |
2 |
0 |
0 |
T56 |
5517 |
1 |
0 |
0 |
T59 |
22886 |
1 |
0 |
0 |
T111 |
6501 |
1 |
0 |
0 |
T112 |
9655 |
1 |
0 |
0 |
T115 |
3362 |
2 |
0 |
0 |
T116 |
4039 |
1 |
0 |
0 |
T117 |
8380 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
89552 |
0 |
0 |
T1 |
371423 |
964 |
0 |
0 |
T2 |
238384 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
136867 |
0 |
0 |
0 |
T5 |
138985 |
149 |
0 |
0 |
T10 |
0 |
834 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
18972 |
0 |
0 |
0 |
T18 |
1140 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
14354 |
9 |
0 |
0 |
T21 |
2109 |
0 |
0 |
0 |
T22 |
9096 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12424417 |
89193 |
0 |
0 |
T1 |
166142 |
965 |
0 |
0 |
T2 |
508 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
305 |
0 |
0 |
0 |
T5 |
541 |
149 |
0 |
0 |
T10 |
0 |
834 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
1589 |
0 |
0 |
0 |
T18 |
83 |
0 |
0 |
0 |
T19 |
137 |
0 |
0 |
0 |
T20 |
49 |
9 |
0 |
0 |
T21 |
153 |
0 |
0 |
0 |
T22 |
663 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173334352 |
89024 |
0 |
0 |
T1 |
185381 |
964 |
0 |
0 |
T2 |
119152 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
35507 |
0 |
0 |
0 |
T5 |
69372 |
149 |
0 |
0 |
T10 |
0 |
823 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
9474 |
0 |
0 |
0 |
T18 |
517 |
0 |
0 |
0 |
T19 |
991 |
0 |
0 |
0 |
T20 |
7130 |
9 |
0 |
0 |
T21 |
988 |
0 |
0 |
0 |
T22 |
5243 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12424417 |
88674 |
0 |
0 |
T1 |
166142 |
965 |
0 |
0 |
T2 |
508 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
305 |
0 |
0 |
0 |
T5 |
541 |
149 |
0 |
0 |
T10 |
0 |
823 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
1589 |
0 |
0 |
0 |
T18 |
83 |
0 |
0 |
0 |
T19 |
137 |
0 |
0 |
0 |
T20 |
49 |
9 |
0 |
0 |
T21 |
153 |
0 |
0 |
0 |
T22 |
663 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
86666551 |
88114 |
0 |
0 |
T1 |
926898 |
963 |
0 |
0 |
T2 |
59576 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
17755 |
0 |
0 |
0 |
T5 |
34686 |
149 |
0 |
0 |
T10 |
0 |
787 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
4737 |
0 |
0 |
0 |
T18 |
258 |
0 |
0 |
0 |
T19 |
496 |
0 |
0 |
0 |
T20 |
3565 |
9 |
0 |
0 |
T21 |
494 |
0 |
0 |
0 |
T22 |
2619 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12424417 |
87774 |
0 |
0 |
T1 |
166142 |
964 |
0 |
0 |
T2 |
508 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
305 |
0 |
0 |
0 |
T5 |
541 |
149 |
0 |
0 |
T10 |
0 |
787 |
0 |
0 |
T11 |
0 |
232 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
1589 |
0 |
0 |
0 |
T18 |
83 |
0 |
0 |
0 |
T19 |
137 |
0 |
0 |
0 |
T20 |
49 |
9 |
0 |
0 |
T21 |
153 |
0 |
0 |
0 |
T22 |
663 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
106821 |
0 |
0 |
T1 |
396512 |
1150 |
0 |
0 |
T2 |
248325 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
142574 |
0 |
0 |
0 |
T5 |
180782 |
221 |
0 |
0 |
T10 |
0 |
977 |
0 |
0 |
T11 |
0 |
280 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
20184 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1974 |
0 |
0 |
0 |
T20 |
26952 |
33 |
0 |
0 |
T21 |
2197 |
0 |
0 |
0 |
T22 |
9476 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
148 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11945827 |
106458 |
0 |
0 |
T1 |
166334 |
1150 |
0 |
0 |
T2 |
508 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
305 |
0 |
0 |
0 |
T5 |
613 |
221 |
0 |
0 |
T10 |
0 |
977 |
0 |
0 |
T11 |
0 |
280 |
0 |
0 |
T12 |
0 |
72 |
0 |
0 |
T17 |
1589 |
0 |
0 |
0 |
T18 |
83 |
0 |
0 |
0 |
T19 |
137 |
0 |
0 |
0 |
T20 |
73 |
33 |
0 |
0 |
T21 |
153 |
0 |
0 |
0 |
T22 |
663 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
148 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
178931655 |
105596 |
0 |
0 |
T1 |
189752 |
1122 |
0 |
0 |
T2 |
119198 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
68437 |
0 |
0 |
0 |
T5 |
95417 |
257 |
0 |
0 |
T10 |
0 |
924 |
0 |
0 |
T11 |
0 |
292 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T17 |
9554 |
0 |
0 |
0 |
T18 |
574 |
0 |
0 |
0 |
T19 |
947 |
0 |
0 |
0 |
T20 |
12937 |
33 |
0 |
0 |
T21 |
1055 |
0 |
0 |
0 |
T22 |
4548 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12453125 |
104962 |
0 |
0 |
T1 |
166310 |
1122 |
0 |
0 |
T2 |
508 |
109 |
0 |
0 |
T3 |
0 |
27 |
0 |
0 |
T4 |
305 |
0 |
0 |
0 |
T5 |
649 |
257 |
0 |
0 |
T10 |
0 |
924 |
0 |
0 |
T11 |
0 |
292 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T17 |
1589 |
0 |
0 |
0 |
T18 |
83 |
0 |
0 |
0 |
T19 |
137 |
0 |
0 |
0 |
T20 |
73 |
33 |
0 |
0 |
T21 |
153 |
0 |
0 |
0 |
T22 |
663 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T105 |
0 |
112 |
0 |
0 |