Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	164868292	5293800	0	0
clk_enables_rd_A	164868292	45450	0	0
clk_hints_rd_A	164868292	39583	0	0
extclk_ctrl_rd_A	164868292	49645	0	0
extclk_ctrl_regwen_rd_A	164868292	37105	0	0
jitter_enable_rd_A	164868292	54204	0	0
jitter_regwen_rd_A	164868292	41275	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	5293800	0	0
T1	396705	141264	0	0
T2	124162	0	0	0
T4	136867	0	0	0
T5	192824	0	0	0
T10	0	40495	0	0
T15	0	194390	0	0
T17	1134	0	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T30	0	58200	0	0
T42	0	87350	0	0
T60	0	42301	0	0
T61	0	99348	0	0
T62	0	131041	0	0
T63	0	112526	0	0
T64	0	39458	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	45450	0	0
T10	132803	889	0	0
T24	66133	0	0	0
T27	37741	0	0	0
T64	0	1069	0	0
T78	1112	0	0	0
T98	1511	0	0	0
T99	1475	0	0	0
T100	2022	0	0	0
T101	1025	0	0	0
T102	1888	0	0	0
T103	2088	0	0	0
T125	0	6	0	0
T126	0	4	0	0
T127	0	1067	0	0
T128	0	3	0	0
T129	0	3419	0	0
T130	0	2	0	0
T131	0	1428	0	0
T132	0	8	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	39583	0	0
T10	132803	648	0	0
T24	66133	0	0	0
T27	37741	0	0	0
T64	0	798	0	0
T78	1112	0	0	0
T98	1511	0	0	0
T99	1475	0	0	0
T100	2022	0	0	0
T101	1025	0	0	0
T102	1888	0	0	0
T103	2088	2	0	0
T125	0	15	0	0
T126	0	3	0	0
T127	0	1109	0	0
T128	0	1	0	0
T129	0	2930	0	0
T130	0	4	0	0
T131	0	1269	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	49645	0	0
T3	21245	0	0	0
T4	136867	0	0	0
T10	0	925	0	0
T19	1894	32	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	46	0	0
T26	51018	61	0	0
T27	0	79	0	0
T28	2099	0	0	0
T32	916	0	0	0
T34	1050	0	0	0
T79	0	11	0	0
T100	0	34	0	0
T133	0	42	0	0
T134	0	2	0	0
T135	0	52	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	37105	0	0
T3	21245	0	0	0
T10	132803	594	0	0
T26	51018	47	0	0
T27	37741	54	0	0
T28	2099	0	0	0
T32	916	0	0	0
T33	1159	0	0	0
T34	1050	0	0	0
T40	0	8	0	0
T64	0	750	0	0
T77	2208	0	0	0
T97	1601	0	0	0
T127	0	885	0	0
T129	0	2687	0	0
T131	0	1285	0	0
T136	0	15	0	0
T137	0	27	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	54204	0	0
T10	132803	976	0	0
T24	66133	0	0	0
T27	37741	0	0	0
T64	0	1010	0	0
T78	1112	0	0	0
T98	1511	0	0	0
T99	1475	0	0	0
T100	2022	0	0	0
T101	1025	0	0	0
T102	1888	0	0	0
T103	2088	65	0	0
T125	0	135	0	0
T126	0	95	0	0
T127	0	1313	0	0
T128	0	113	0	0
T129	0	3301	0	0
T130	0	103	0	0
T131	0	1844	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164868292	41275	0	0
T10	132803	792	0	0
T24	66133	0	0	0
T27	37741	0	0	0
T64	0	908	0	0
T78	1112	0	0	0
T98	1511	0	0	0
T99	1475	0	0	0
T100	2022	0	0	0
T101	1025	0	0	0
T102	1888	0	0	0
T103	2088	0	0	0
T127	0	1230	0	0
T129	0	3102	0	0
T131	0	1426	0	0
T138	0	5923	0	0
T139	0	2555	0	0
T140	0	1404	0	0
T141	0	3940	0	0
T142	0	3492	0	0